Chap'4 Failure Mechanisms

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Chap.4 Failure Mechanisms

• Most ICs contain subtle flaws ? leads to
  eventual failure
• Testing can not find every design flaw ?
  Layout designer must find/eliminate as many
  flaws as possible.

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Chap.4 Failure Mechanisms

• Most ICs contain subtle flaws ? leads to
  eventual failure
• Testing can not find every design flaw ?
  Layout designer must find/eliminate as many
  flaws as possible.

• Electrical Overstress, EOS EOS failure due to
  too high voltage or current
• ESD, Electrostatic Discharge
• Electromigration slow wear-out of wires
• Dielectric Breakdown
• Antenna effect charge accumulation on conductors
  during processing (etching, ion implantation)

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• 2. Contamination- corrosion, mobile ions, etc.
• Dry corrosion Al metal under moisture ionic
  contaminants gt minimize and size of PO
  openings
• mobile ion contamination e.g., Na ions gt
  Phosphorus stabilization of Vt immobilizes alkali
  ions

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• 2. Contamination- corrosion, mobile ions, etc.
• Dry corrosion Al metal under moisture ionic
  contaminants gt minimize and size of PO
  openings
• mobile ion contamination e.g., Na ions gt
  Phophorus stabilization of Vt immobilizes alkali
  ions

3. Surface Effects- Hot carrier injection hot
carriers in pinched off region can generate e-h
pairs by impact ionization. ..gt reduce
E-field within pinchoff regionNote no
injection when MOSFET is under cutoff or linear
mode (Digital) injection under saturation mode
(some analog circuits have MOSFETs under
continuously saturation mode.)
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• 1.1 ESD
• Static charges on human body can produce 10,000
  V on a small capacitor.
• Discharge of lt50 V can destroy gate dielectric
  it is so small that it is unnoticeable, casual
  activity can do this.

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• 1.1 ESD
• Static charges on human body can produce 10,000
  V on a small capacitor.
• Discharge of lt50 V can destroy gate dielectric
  it is so small that it is unnoticeable, casual
  activity can do this.

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• 1.1 ESD
• Static charges on human body can produce 10,000
  V on a small capacitor.
• Discharge of lt50 V can destroy gate dielectric
  it is so small that it is unnoticeable, casual
  activity can do this.

Ex) 2kV HBM C150 pF 150 x 1E-12 Coul/V V
2,000 V Q CV 1.5E2 x 1E-12 x 2E3 Coul 3E-7
Coul 3E-7/1.6E-19 electrons 2E12 e
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• 1.1 ESD
• Static charges on human body can produce 10,000
  V on a small capacitor.
• Discharge of lt50 V can destroy gate dielectric
  it is so small that it is unnoticeable, casual
  activity can do this.

• Vulnerable device (regions) small-area
  diffusions such as EBJ of NPN, MOS gates,
• deposited capacitor electrodes, etc. ?
  prevention
• employ protection devices which are connected to
  the bond pads of vulnerable pins.

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(C ) CDM Charged Device Model

• Place IC package upside-down on grounded metal
  plate.
• Charge the IC package to a specified voltage thru
  a large R
• Discharge one pin to a low-impedance ground ?
  produces briefpulses of very high current,
  typical 1-1.5 kV CDM

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• 1.3 Dielectric breakdown
• 5V CMOS and BiCMOS use 20nm oxide
• 1.8V CMOS uses 9nm oxide.
• Oxides with lt4.5nm thickness can have direct
  tunneling, and
• thicker oxides by trap-assisted tunneling or
  Fowler-Nordheim tunneling.

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• 1.3 Dielectric breakdown
• 5V CMOS and BiCMOS use 20nm oxide
• 1.8V CMOS uses 9nm oxide.
• Oxides with lt4.5nm thickness can have direct
  tunneling, and
• thicker oxides by trap-assisted tunneling or
  Fowler-Nordheim tunneling.

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• 1.3 Dielectric breakdown
• 5V CMOS and BiCMOS use 20nm oxide
• 1.8V CMOS uses 9nm oxide.
• Oxides with lt4.5nm thickness can have direct
  tunneling, and
• thicker oxides by trap-assisted tunneling or
  Fowler-Nordheim tunneling.

• Maximum stress allowed is 3.5-4 MV/cm for
  30-50nm oxides, and
• 4-4.5MV/cm for thinner oxides.

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1.4 Antenna effect Dry etching has ions whose
charge can accumulate on any exposed conductor
on the wafer surface ? if thin gate oxide (GOX)
is underneath, the GOX can breakdown.
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1.4 Antenna effect Dry etching has ions whose
charge can accumulate on any exposed conductor
on the wafer surface ? if thin gate oxide (GOX)
is underneath, the GOX can breakdown. How to
prevent - reduce the size of charge gettering
conductor (antenna ratio) by employing metal
jumper (Fig.4.3)
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How to prevent Antenna Effect, contd.
- connect excessive antenna ratio metal nodes to
S/D diffusions of MOSFET or using a leaker
(fig.4.4) because if tox gt 40nm ? S/D junctions
avalanche before oxide breakdown, and leaks away
the accumulated charge on metal. - Thin
oxides (lt40nm) use the forward biasing of
NSD/pepi or PSD/nwell leakers
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2. Contamination1.1 dry corrosion Al metal
under moisture ionic contaminants gt minimize
and size of PO openings
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2. Contamination1.1 dry corrosion Al metal
under moisture ionic contaminants gt minimize
and size of PO openings 1.2 mobile ion
contamination e.g., Na ions . They are mobile
in Oxides!!
charges are Alkali ions (Na ions, in particular)
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1.2 mobile ion contamination How To Prevent gt
Phophorus in Poly and in PO immobilizes alkali
ions (Na) and stabilizes Vt This Phophorus
stabilization protects from above (or top)
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1.2 mobile ion contamination How To Prevent gt
Phophorus in Poly and in PO immobilizes alkali
ions (Na) and stabilizes Vt This Phophorus
stabilization protects from above (or top)
gt Alkali ions can enter and move in any exposed
ILO and FOX. Scribe Seal protects the side
edge of ILO and FOX at the periphery of die.