Virtual Memory Minggu 12

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Virtual Memory(Minggu 12)
IKI 30210 Organisasi Sistim Komputer Fakultas
Ilmu KomputerUniversitas Indonesia
Johny Moningka (moningka_at_cs.ui.ac.id),
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Memory System

• Teknologi dan Sistem Memori
• Review teknologi memori
• Rancangan Memory Hierarchy
• Cache Memory Design Analysis
• Main Memory Virtual Memory

3
Memory Hierarchy
Regs
Upper Level
Instr. Operands
Faster
Cache
Blocks
L2 Cache
Blocks
Memory
Pages
Disk
Files
Larger
Tape
Lower Level
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Memory Hierarchy

• Menurut Principle of Locality gt cache
  memberikan kecepatan akses cache memory dan
  besarnya memory seperti ukuran DRAM memory,
• Secara rekursif prinsip ini dapat diterapkan
  untuk level berikutnya yakni speed of DRAM
  memory, size of Disk memory/storages.
• Hal yang lain dari sistem memori? Pengaruh
  terhadap program gt proses yang sedang berjalan
• Dukungan apa saja yang diperlukan untuk program
  yang aktif dan berada di memory (live)?

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Multi-tasking Requirements

• Share memory antara multipel proses, tapi
  terdapat proteksi antar proses
• Proses tidak dapat mengakses bagian memory yang
  tidak menjadi haknya (privilege).
• Efektif untuk penerapan dan perlindungan OS dalam
  manajemen resources.
• Address space give each program the illusion
  that it has its own private memory
• Suppose code starts at address 0x40000000. But
  different processes have different code, both
  residing at the same address.
• So each program has a different view of memory.

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Virtual Memory

• Disebut Virtual Memory
• Program (proses) mempunyai memory (address space)
  sendiri
• Mendukung kapasitas memory yang lebih besar dari
  yang sebenarnya (DRAM) gt menyamai kapasitas pada
  lower level (disk)
• Juga memungkinkan OS share memory antar proses,
  proteksi program terhadap program lain
  (multi-programming)
• Saat ini peranan manajemen memory yang efisien
  dan efektif utk proteksi lebih penting
  dibandingkan sebagai memori hirakis

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Virtual to Physical Addr. Translation
Program operates in its virtual address space
Physical memory (incl. caches)
HW mapping
virtual address (inst. fetch load, store)
physical address (inst. fetch load, store)

• Each program operates in its own virtual address
  space only program running
• Each is protected from the other
• OS can decide where each goes in memory
• Hardware (HW) provides virtual ? physical mapping

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Address Spaces

• Virtual and physical address spaces divided into
  equal-sized blocks
• Pages (both virtual and physical)
• Virtual address space typically larger than
  physical
• Each process has separate virtual address space

Physical addresses (PA)
Virtual addresses (VA)
0
address translation
0
VP 1
PP2
Process 1
VP 2
N-1
(Read-only library code)
PP7
0
Process 2
VP 1
VP 2
PP10
N-1
M-1
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Contoh (early systems) Register

User C
User B

• Diperlukan mapping tidak perlu sinambung
• Process size gtgt mem
• Model direct register tidak memadai gt gunakan
  indirection (hw mapping/pointer/table)

User A
OS
0
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Mapping Virtual Memory to Physical Memory
Virtual Memory

• Divide into equal sizedchunks (about 4 KB - 8 KB)

Stack

• Any chunk of Virtual Memory assigned to any
  chunck of Physical Memory (page)

Physical Memory
64 MB
0
0
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Paging Organization (assume 1 KB pages)
Page is unit of mapping
Page also unit of transfer from disk to physical
memory
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Mapping Function (1)

• Tidak dapat mempunyai fungsi sederhana untuk
  memprediksi mapping dari VA ke PA
• Virtual Page dari VA dapat menempati sembarang
  Physical Page dari PA (tidak ada pembatasan)
• Fleksibilitas alokasi page tergantung kebutuhan
  (demand) dari proses atau OS
• OS dapat mengganti page di memory gt swap ke disk
• Page dapat di reload pada lokasi mana saja di
  physical memory.

Use table lookup (Page Table) for mappings
Page number is index
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Mapping Function (2)

• Virtual Memory Mapping Function
• Physical Offset Virtual Offset
• Posisi byte (address) dalam satu page sama antara
  VA dan PA (ukuran page harus sama)
• Physical Page Number PageTableVirtual Page
  Number
• Terdapat mapping (translation) dari virtual page
  ke physical page
• (P.P.N. also called Page Frame)

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Address Mapping Page Table
Page Table located in physical memory
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Address Translation via Page Table
virtual address
page table base register
n1
0
p1
p
virtual page number
page offset
VPN acts as table index
access
valid
physical page number
Address
if valid0 then page not in memory
0
p1
p
m1
physical page number
page offset
physical address
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Page Table

• Page Table struktur OS yang berisi informasi
  mapping dari virtual addresses ke physical
  locations
• Tergantung implementasi software (OS) mengatur
  data struktur tsb
• Setiap proses mempunyai page table sendiri
• Proses state Program Counter, all registers,
  plus page table
• OS memberikan page tables ke suatu proses dengan
  mengubah Page Table Base Register

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VM Requirements Modern OS

• Motivasi VM Manajemen Memori
• Sharing memori proteksi
• Sharing Physical memory (pages) dapat
  dialokasikan pada berbagai proses
  (multi-programming)
• Proteksi Proses hanya dapat menggunakan pages yg
  ditunjuk oleh page table dari proses tersebut
• Separate address spaces
• Memudahkan programming program menggunakan
  virtual address, tidak ada batasan address yang
  dapat digunakan oleh program
• What about the memory hierarchy?

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Paging/Virtual Memory Multiple Processes
User B Virtual Memory
User A Virtual Memory


Physical Memory
Stack
Stack
64 MB
Heap
Heap
Static
Static
0
Code
Code
0
0
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Page Table Entry (PTE) Format

• PTE gt Physical Page Number atau indikasi page
  tersebut tidak ada di Main Memory
• OS maps to disk if Not Valid (V 0)

• If valid, also check if have permission to use
  page Access Rights (A.R.) may be Read Only,
  Read/Write, Executable etc.

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Page Table Operation

• Translation
• Separate (set of) page table(s) per process
• VPN forms index into page table
• Computing Physical Address
• Page Table Entry (PTE) provides information
  about page
• Valid bit 1 gt page in memory.
• Use physical page number (PPN) to construct
  address
• Valid bit 0 gt page in secondary memory
• Page fault
• Must load into main memory before continuing
• Checking Protection
• Access rights field indicate allowable access
• E.g., read-only, read-write, execute-only
• Typically support multiple protection modes
  (e.g., kernel vs. user)
• Protection violation fault if dont have
  necessary permission

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VM design issues

• Everything Driven by Enormous Cost of Misses
• Hundreds of thousands to millions of clocks.
• vs units or tens of clocks for cache misses.
• Disks are high latency
• Typically 10 ms access time
• Moderate disk to memory bandwidth
• 10 MBytes/sec transfer rate
• Large Block Sizes
• Typically 1KB16 KB
• Amortize high access time
• Reduce miss rate by exploiting spatial locality
• Perform Context Switch While Waiting
• Memory filled from disk by direct memory access
• Meanwhile, processor can be executing other
  processes

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VM design issues (cont)

• Fully Associative Page Placement
• Eliminates conflict misses
• Every miss is a killer, so worth the lower hit
  time
• Use Smart Replacement Algorithms
• Handle misses in software
• Plenty of time to get job done
• Vs. caching where time is critical
• Miss penalty is so high anyway, no reason to
  handle in hardware
• Write Back Only
• Disk access too slow to afford write through

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Comparing the 2 levels of hierarchy

• Versi Cache Versi Virtual Memory
• Block Page
• Miss Page Fault
• Block Size 32-64B Page Size 4K-8KB
• Placement Direct Mapped, Fully
  Associative N-way Set Associative
• Replacement Least Recently UsedLRU or
  Random (LRU)
• Write Thru or Back Write Back

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Integrating VM and cache
miss
VA
PA
Trans- lation
Cache
Main Memory
CPU
hit
data

• Most Caches Physically Addressed
• Accessed by physical addresses
• Allows multiple processes to have blocks in cache
  at same time
• Allows multiple processes to share pages
• Cache doesnt need to be concerned with
  protection issues
• Access rights checked as part of address
  translation
• Perform Address Translation Before Cache Lookup
• But this could involve a memory access itself
• Of course, page table entries can also become
  cached

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VM Problem 1

• Map every address ? 1 indirection via Page Table
  in memory per virtual address ? 1 virtual
  memory accesses 2 physical memory accesses ?
  LAMBAT!
• Observasi sebab lokalitas dari pages data
  (program), maka terdapat lokalitas juga virtual
  address translations dari pages yg diakses oleh
  program.
• Gunakan cache kecil utk menyimpan translasi yg
  dilakukan sebelumnya.
• Mapping cache Translation Lookaside Buffer, or
  TLB

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Translation Look-Aside Buffers (TLBs)

• TLBs berukuran kecil (small is faster), tipikal
  128 - 256 entries

hit
PA
miss
VA
TLB Lookup
Cache
Main Memory
Processor
miss
hit
Trans- lation
data
On TLB miss, get page table entry from main memory
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Address translation with a TLB
TLB
Cache
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Typical TLB Format
Virtual Physical Dirty Ref Valid Access Page
Number Page Number Rights

• TLB just a cache on the page table mappings
• TLB access time comparable to cache (much
  less than main memory access time)
• Dirty since use write back, need to know
  whether or not to write page to disk when
  replaced
• Ref Used to help calculate LRU on replacement
• Cleared by OS periodically, then checked to see
  if page was referenced

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What if not in TLB?

• Bagaimana jika terjadi TLB miss?
• Tidak ada entry yg memenuhi VA gt miss
• Kasus 1 Page dari VA berada di memory
• Valid bit 1, jadi retrieve Physical Page Number
  dari page table gt buat entry baru VPN PPN
• Kasus 2 Page dari VA tidak berada di memory
• Valid bit 0, page fault, dukungan hardware
  interrupt ke aktif proses, dan transfer control
  ke OS (context switch proses lain).
• Umumnya page fault terdeteksi pada clock cycle
  mengakses memory gt restart instruksi terakhir
  setelah page fault ditangani.

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What if the data is on disk?

• We load the page off the disk into a free block
  of memory, using a DMA (Direct Memory Access
  very fast!) transfer
• Meantime we switch to some other process waiting
  to be run
• When the DMA is complete, we get an interrupt and
  update the process's page table
• So when we switch back to the task, the desired
  data will be in memory

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Disk / System Interface

• Processor Signals Controller
• Read block of length P starting at disk address X
  and store starting at memory address Y
• Read Occurs
• Direct Memory Access
• Under control of I/O controller
• I / O Controller Signals Completion
• Interrupt processor
• Can resume suspended process

(1) Initiate Block Read
(3) Read Done
(2) DMA Transfer
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What if we dont have enough memory?

• We chose some other page belonging to a program
  and transfer it onto the disk if it is dirty
• If clean (disk copy is up-to-date), just
  overwrite that data in memory
• We chose the page to evict based on replacement
  policy (e.g., LRU)
• And update that program's page table to reflect
  the fact that its memory moved somewhere else
• If continuously swap between disk and memory,
  called Thrashing

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And in conclusion

• Issue utama manajemen main memory gt hubungan
  dengan disk (lower level)
• Prinsip lokalitas memori hirarkis!!!
• Tambahkan proteksi dan sharing gt critical
  utk OS modern.
• Gunakan page table mapping setiap proses
  virtual address ke physical address
• Tambahkan TLB sebagai cache Virtual gt Physical
  addr. Translations gt hit tidak perlu mengakses
  page table
• OS mengatur setiap proses mempunyai pages yg
  cukup (spatial locality) gt mengurangi page
  fault (thrashing) gt out of memory

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... and to remember Memory System

• Programmers View
• Menginginkan address space yang besar (flat)
• Mengalokasikan blok address yang sinambung dan
  sesuai kebutuhan (dinamik) program besar
• Eksklusif Processor owns machine
• Mempunyai private address space
• Tidak terpengaruh oleh proses yang lain
  (proteksi)
• System View
• Gunakan virtual address space yg menunjuk
  (mapping) ke set pages di physical memory
• Tidak perlu sinambung (contiguous)
• Enforce protection saat penerjemahan alamat (VA
  gt PA)
• Alokasikan kebutuhan pages di memory secara
  dinamis
• OS perlu mengatur banyak proses serentak berada
  di memory
• Secra kontinyu melalukan switching antar
  proses-proses tsb.
• Terutama dalam kasus dimana harus menunggur
  resource/event, misalkan terjadi page fault dan
  I/O disk transfer ke main memory.