Introduction to the Balanced Gamma (BG) Switch for Broadband Communications

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Introduction to the Balanced Gamma (BG) Switch
for Broadband Communications
A Presentation for the Advanced Data Networks
(ENGI 9867)

• Presented by
• Cheng Li

The Computer Engineering Research Laboratories
(CERL) Faculty of Engineering and Applied
Science Memorial University of Newfoundland
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Multicast in Broadband Packet Switching Network
Gateway Networks
Network B
Network C
Data Networks
Network D
Network A
Gateway Networks
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High-Speed Packet Switch Classification
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Multicast Switches Classification

• Starlite Switch
• Knockout Switch
• Turners Broadcast Packet Switch
• Lees Multicast Switch
• SCCQ Multicast Switch
• LGMIN Switch
• Multinet Switch

• Recursive Multistage Structured Multicast Switch
• Three-Stage Clos Multicast Switch
• MOBAS Switch
• Abacus Switch
• PINIUM Switch

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General Model for the Packet Switches
CAC Connection Admission Control
SM System Management
CAC
SM
OPC Output Port Controller
IPC Input Port Controller
IPC
OPC
IPC
OPC
Switch Fabric
. . .
. . .
IPC
OPC
SF Switch Fabric
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Switch Fabrics Core of Switching Nodes

• Center part of the whole switching network.
• Hardware implementation is required.
• Less efficient switch fabrics lead to poor
  performance.
• Efficient switch fabrics are characterized by
  their high throughput, low delay, low delay
  jitter, low cell loss, and scalability.

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Target An Innovative High-Performance Multicast
Switch

• Architecture Design
• Architecture Justification
• Routing, Replication and Acknowledgement
• Scalable Architecture

• VLSI Design
• Chip Design
• Simulation and Testing
• Implementation

• Performance Evaluation
• Multicast Traffic Model
• Analytical Modeling
• Performance Analysis

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8 ? 8 Multicast BG Switch Architecture
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OPC Request Probability Distribution under
Multicast Bursty Traffic
Through simulation results. Mean Burst Length is
5, Mean Fanout is 2, Traffic Load is 100
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SE Self-Routing and Self-Replication
Output Link 0
Output Link 1
Output Link 2
Output Link 3
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Dynamic-length Self-Routing Replication
Algorithm for an 8 ? 8 Multicast BG Switch
0010
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A R C H I T E C T U R A L
S C A L A B I L I T Y
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Target An Innovative High-Performance Multicast
Switch

• Architecture Design
• Architecture Justification
• Routing, Replication and Acknowledgement
• Scalable Architecture

• VLSI Design
• Chip Design
• Simulation and Testing
• Implementation

• Performance Evaluation
• Multicast Traffic Model
• Analytical Modeling
• Performance Analysis

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Performance Evaluation

• Under uniform and non-uniform multicast traffic,
  with random and bursty cell arrival.
• Traffic load defined at switch output port
• Offered load to switch output is associated with
  load at the input via mean fanout of multicast
  traffic, i.e.,
• Compared with ideal non-blocking output buffered
  multicast switch and other published switches
• Ideal non-blocking network satisfies all the
  input requests if there is space in the output
  buffer
• Abacus switch and PINIUM switch (Published on
  JSAC97)
• Performance metrics
• Average and Maximum Cell Delay
• Cell Loss Ratio
• Average and Maximum Input / Output Buffer
  Requirements

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Network Traffic Models

• Proper traffic models are critical for
  performance comparison between different
  architectures
• Key aspects in a traffic model
• Traffic load behavior
• Bursty nature and correlation in traffic arrivals
• Traffic destination selection distribution
• Distribution of traffic QoS classes
• Proportion of unicast and multicast traffic and
  their characteristics
• Network Processing Forum (NPF)
• Founded in February 2001 by merging to former
  industrial groups
• Common Programming Interface Forum (CPIX)
• Common Switch Interface Consortium (CSIX)
• Develop benchmark framework for switch design,
  testing, and comparison
• Switch fabric benchmarking framework approved in
  July 2003

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Traffic Type Model



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Multicast Bursty Traffic

• Described by three independent processes
• Arrival process
• ON - OFF Bursty Traffic Model
• Fanout distribution process
• Truncated Geometric Distribution
• Destination selection process
• Random

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Bursty Traffic ON-OFF Model
On Period
Off Period
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Analytical Modeling

• Under multicast random traffic condition
• Random (non-bursty) cell arrival
• Truncated geometric distributed multicast cell
  fanout
• Uniformly distributed cell destination
• Analysis following the three-phase backpressure
  switching operation
• Cell blocking probabilities at SEs of different
  stages as well as for the whole switch fabric are
  analyzed
• Output queue analysis using discrete-time Markov
  chain
• Input queuing analysis using discrete-time Markov
  chain
• Obtain overall performance measures

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Finite Input Queue Analysis
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Loss Performance Comparison

• Traffic condition
• Switch Size 128 x 128 Traffic Load 90
  Mean Fanout 2 Output Buffer 500 Duration One
  Billion cells

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Loss Performance Under MBT

• Traffic condition
• Switch Size 128 x 128 Traffic Load 90
  Burstiness 5 Output Buffer 3000 Duration One
  Billion cells

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Delay Performance Under MBT

• Traffic condition
• Traffic Load 90 Fanout 2 Burstiness 5 IB
  Size 300 OB Size 3000 Duration One Billion
  cells

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Target An Innovative High-Performance Multicast
Switch

• Architecture Design
• Architecture Justification
• Routing, Replication and Acknowledgement
• Scalable Architecture

• VLSI Design
• Chip Design
• Simulation and Testing
• Implementation

• Performance Evaluation
• Multicast Traffic Model
• Analytical Modeling
• Performance Analysis

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Digital IC Design Flow From CMC
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DesignandImplementation
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SwitchElement(4 x 4)Architecture
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Switch Element Functional Simulation
Example shown for SEs at Stage 0 of 16 x 16 BG
switch
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Multicast BG Switch Functional Testing

• Not possible to verify results through waveform
  observation, alternative approach must be used
• Testing Methodology
• Data files are used by testbench file for
  multicast BG switch to emulate input/output
  buffers
• During HW simulation, Tag, ACK, and Payload
  information at switch input and output are
  recorded in files during each switching cycle for
  future analysis
• High level language (C/C) is used to generate
  data randomly as well as analyze HW simulation
  results

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VLSI Design

• Implemented using 0.18 µm CMOS technology
• Hardware complexity and Timing
• Switch (16 x 16) synthesized using 5 ns clock,
  which yield an aggregated switching capacity for
  single plane 16 x 16 BG Multicast switch at
  around 3.2 Gbps
• Stage components are synthesized under the same
  clock for hardware complexity estimation for
  larger switch sizes
• Core logic area in square microns is converted to
  gate count via two-input nAND gate

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Hardware Complexity
Synthesized result for 16 x 16 multicast BG
switch (in gates)
Estimated result for Larger switches
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Conclusions

• New implicit multicast switch architecture
• New self-routing and replication algorithm and
  acknowledgement algorithm
• Outstanding performance of the multicast BG
  switch
• Analytical modeling for performance analysis
• Realizable and scalable switch architecture