HIGH SPEED, PLUGGABLE OPTICAL BACKPLANE CONNECTOR TECHNOLOGY

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HIGH SPEED, PLUGGABLE OPTICAL BACKPLANE
CONNECTOR TECHNOLOGY
Richard Pitwon, Ken Hopkins, Dave Milward Xyratex
Technology Ltd
International Symposium on Photonic
Packaging Electrical Optical Circuit Board and
Optical Backplane organized by Fraunhofer IZM
VDI/VDE-IT Munich, Germany November 2006
David R. Selviah, Ioannis Papakonstantinou Kai
Wang, F. Anibal Fernández University College
London (UCL)
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THE STORLITE PROJECT
Purpose British government funded initiative to
investigate incorporation of optical backplanes
into high bandwidth systems and develop solutions
Duration June 2003 November 2005
Xyratex Investigation into optical backplane
connector technology and prototype solution
development
Exxelis Ltd Optical PCB manufacture
University College London Investigation into
performance enabling polymer waveguide structures
and characterisation
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RESEARCH OBJECTIVES

• Investigation of current state of the art in
  optical PCB technology research
• Polymeric waveguide fabrication and
  characterisation
• Optical PCB Design Rules
• Investigation into low-cost technology drivers
• Method of pluggable daughtercard connection to an
  optical backplane
• Development of prototype solutions
• Parallel optical transceiver and pluggable
  optical backplane connector
• Development of prototype demonstration assembly

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RESEARCH AND DEVELOPMENT OVERVIEW

• High speed parallel optical transceiver
• Opto-mechanical registration interface
• Low-cost optical backplane connection mechanism
• Low cost precision optical alignment and assembly
  method
• Optical PCB interface coupling method
• Prototype demonstration unit

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HIGH BANDWIDTH BACKPLANE ENVIRONMENTS
16 Drive EBOD Storage System
12 Drive SBOD Storage System
48 Drive RAID Storage System
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HIGH BANDWIDTH BACKPLANE
Dual Port Disk Drives
Power Module
Air Flow Channels
High Speed Connectors To Controllers
Controller Module
Multi Layer Interconnect Backplane
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BACKPLANE ENGAGEMENT MODEL
Orthogonal daughtercard engagement to backplane
Embedded optical channels to carry high speed
serial signals between cards
Copper layers to carry power, control signals and
low speed signals
High bandwidth backplane
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PROPOSED COUPLING PRINCIPLE
Surface emitting photonics used on daughtercard
interface
Butt-coupling scheme allows for minimum number of
intermediary optical interfaces
Optical Waveguides
Copper Traces
Backplane
Copper Planes
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PARALLEL OPTICAL TRANSCEIVER DESIGN

• Quad duplex parallel optical transceiver
• 10.3 Gbps per channel (82 Gb/s aggregate
  bandwidth)
• Electronic daughtercard connector
• Flexible and rigid PCB sections
• Optical backplane interface

Active opto-mechanical coupling interface
Rigid optical interface
Rigid base section
Electronic connector
Flexible mid-section
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PHOTONIC INTERFACE DESIGN
PIN Array
Source Microsemi Corporation
VCSEL Array
Source ULM Photonics GmbH
MT compatible interface
GRIN Lens Array
Source GRINTech GmbH
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OPTOELECTRONIC PCB WITH MT SOCKET INTERPOSER
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MT - SOCKET INTERPOSER ON THE TOP OF BACKPLANE
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ACTUAL ALIGNMENT OF THE COMPONENT
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SUPPORT DAUGHTERCARD DESIGN

• 4 Port 10 GbE LAN Physical Relay board

Transceiver receptacle
PCB materialRogers 4350 on outer layers
Host interface
4 XFP ports
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CHARACTERISATION SETUP
Physical layer relay board
MT patchcord for stand alone testing

• Test traffic 10 GbE LAN (10.3 Gbps)
• VCSEL bias current 11.91 mA
• VCSEL modulation current 9.8 mA
• Divergence 25
• Output optical power 0.43 mW
• Average optical jitter 31.2 ps (Pk Pk)

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CONNECTOR MECHANISM
Principal Function Elevation and retraction of
optical interface
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ALIGNMENT METHOD BASED ON MT CONCEPT
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POLYMER OPTICAL WAVEGUIDE TECHNOLOGY
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POLYMER WAVEGUIDE CHARACTERISTICS
Waveguide Material UV-curable polymeric acrylate
(Truemode) Propagation loss _at_ 850 nm 0.04
dB/cm Heat degradation resilience up to 350C
Waveguide properties Size 70 µm x 70 µm Core
index 1.556 Cladding index 1.526 Numerical
aperture 0.302
Waveguide Array Centre to centre pitch 250 µm
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PROTOTYPE DEMONSTRATOR CONSTRUCTION
Passive Electrical Backplane
Separate passive electrical backplane
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PROTOTYPE DEMONSTRATOR CONSTRUCTION
Daughtercard Guide Features
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PROTOTYPE DEMONSTRATOR CONSTRUCTION
Daughtercard Power Supply
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PROTOTYPE DEMONSTRATOR CONSTRUCTION
Daughtercard to Optical Backplane Coupling
Evaluation
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PROTOTYPE DEMONSTRATOR CONSTRUCTION
Optical Backplane Integration
Separate optical PCB
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PROTOTYPE DEMONSTRATOR CONSTRUCTION
Complete Demonstration Unit
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TEST AND CHARACTERISATION
Optical Coupling Characterisation Test traffic
10 GbE LAN (10.3 Gbps) Wavelength 850 nm
Arrangement Active connector waveguide -
patchcord
Reference Signal No Waveguide Jitter 0.34
UI Relative Loss 0 dB
Multimode MT fibre patchcord
10 cm Waveguide with Isapropanol Jitter 0.36
UI Relative Loss 4.5 dB
10 cm Waveguide Diced and Polished Jitter 0.56
UI Relative Loss 6.9 dB
10 cm Waveguide Diced Only Jitter 0.89
UI Relative Loss 7.9 dB
Active prototype connector
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TEST AND CHARACTERISATION
High Speed Network Link Evaluation
Arrangement Test traffic source (10 GbE
LAN) Fibre cable XFP Port 1 (Rx) Daughtercard
1 Connector 1 (Tx) Optical PCB Connector 2
(Rx) Daughtercard 2 XFP Port 2 (Tx) Fibre
cable Traffic Capture
Bit Error Rate lt 10-12
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CONTOUR MAP OF VCSEL AND PD MISALIGNMENT

• (a) Contour map of relative insertion loss
  compared to the maximum coupling position for
  VCSEL misalignment at z 0.

(b) Same for PD misalignment at z 0. Resolution
step was ?x ?y 1 µm.

• Dashed rectangle in the middle of the maps
  corresponds to the expected relative insertion
  loss according to the calculated misalignments
  along x and y in text slides.
• The minimum insertion loss was 4.4 dB,
  corresponded to x 0, y 0, z 0

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TOLERANCES ALONG X, Y AND Z FOR CONNECTOR
COMPONENTS
X y Z
MT-plug ?3 µm (pin-to-pin) ?3 µm (pin-to-GRIN) ________
MT-socket ?3 µm (hole-to-hole) ?3 µm (hole-to-waveguide) ________
OPCB features 2.5 µm (increase in registration wall-to-wall spacing due to overexposure) ?2.5 µm (due to 5 µm extra spacing between feet of interposer) ?1 µm (core thickness control) 10 µm (accuracy of dicing in respect to the dicing lines on the board) 2.5 µm (backstop shift due to overetching)
Tolerance of MT interposer socket to waveguides ?8 µm or ?3 µm if overexposure widening is known and reproducible ?4 µm 12.5 µm or 10 µm if overexposure widening is known and reproducible
Combined tolerance of VCSEL and PIN to waveguides ?11 µm or ?6 µm if overexposure widening is known and reproducible ?7 µm 12.5 µm or 10 µm if overexposure widening is known and reproducible
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RELATIVE INSERTION LOSS OF VCSEL AND PD AS THEY
MOVE AWAY FROM THE OPCB WAVEGUIDES.
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CROSSTALK MEASUREMENT 1
Power received at the end of 0th waveguide as a
function of the lateral distance of the VCSEL
from its center. The boundaries and the centers
of the waveguides on the backplane are marked. In
the cladding power drops at a rate of 0.011 dB/µm
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CROSSTALK MEASUREMENT 2
Signal-to-cross-talk (SCR) levels that 0th
waveguide experiences from its adjacent
waveguides.
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CROSSTALK MEASUREMENT 3
SCR experienced by waveguides number 1 and 4 and
of waveguides number 2 and 3 from the array of
four in the connector if all are in use.
Dashed-dot lines determine the boundaries of the
maximum expected cross-talk based on current
connector tolerances.
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STABILITY TESTING OF THE MT SOCKET INTERPOSER 1
Insertion loss and signal to cross-talk (SCR) as
a function of mating cycle for 75 engagements.
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STABILITY TESTING OF THE MT SOCKET INTERPOSER 2
Histogram of insertion loss
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THE CANDEO PROJECT
Purpose Industrial collaborative effort to
develop commercial technology drivers for optical
backplane and connector technology and drive the
proliferation of optical backplane technology
into the industrial sector
Xyratex Commercial development of proprietary
parallel optical transceiver technology
Samtec Commercial development of optical
backplane engagement mechanism
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CANDEO CURRENT STATUS
Phase I (currently underway)

• High speed parallel optical transceiver design
  modified for commercial design
• Single stage optical backplane engagement
  mechanism developed
• Commercial form factor module designed and
  developed
• First mechanical prototype on exhibition by
  Samtec and Xyratex at Electronica 2006, Samtec
  booth 419 in Hall B4

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INTEGRATED OPTICAL AND ELECTRONIC PCB
MANUFACTURING
Purpose To compare multimode, polymer waveguide
manufacture techniques for large area optical
backplanes and to develop design rules.
Academic Partners University College London
(UCL) Waveguide design, modelling,
measurement Heriot-Watt University Direct UV
laser waveguide fabrication Loughborough
University Laser ablation, surface treatment,
printing waveguide fabrication,
flip-chip assembly Industrial Partners Xyratex
End user and project manager BAE Systems End
user Renishaw End user Exxelis Polymer
chemistry, lithographic waveguide
fabrication Cadence PCB layout tools Rsoft
Design Optical modeling tools Xaar print head
technology
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SUMMARY

• Xyratex White Papers
• An Optical Backplane Connection System with
  Pluggable Active Board Interfaces
• (available from Xyratex website)
• Pluggable Optical Backplane Connector Technology
  (available)
• Optical vs Copper Cost and Performance
  Evaluation (pending)
• www.xyratex.com

Intellectual Property 7 patent applications
related to optical PCB interconnect and
communication structures and methodologies
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SUMMARY

• UCL Publications (available from UCL website)
• Papers published on waveguide devices
• Sources misalignment x, y, z
• Detector misalignment x, y, z
• Straight tapered waveguide
• Bends
• Propagation loss
• Thermal optics switch
• Power splitter

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Acknowledgements UK Department of Trade and
Industry EPSRC Exxelis Dr Navin Suyal Prof.
Frank Tooley
Thank You for Your Attention
Richard C A Pitwon Senior Photonics Engineer Ken
Hopkins Hardware Architect Dave
Milward Development Manager E-mail
rpitwon_at_xyratex.com
David R Selviah F. Anibal Fernández Senior
Academics Ioannis Papakonstantinou Postgraduate
Researcher Kai Wang Research Fellow E-mail
d.selviah_at_ee.ucl.ac.uk
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