EEL 4768 Computer System Design II Lecture 2 Von Neumann Model

1
EEL 4768Computer System Design IILecture 2Von
Neumann Model

• Prof. Taskin Kocak
• http//www.cs.ucf.edu/tkocak/eel4768.html

2
Computer Organization (Von Neumann)

• The architecture of a computer system is what the
  user sees or has access to.
• The structure is called the implementation.
• Von Neumann ISA (Instruction Set Architecture) is
  first described in 1946.
• Von Neumann ISA is an accumulator based ISA
  similar to Motorola 68HC11 used in EEL4767.
• Instructions, data and I/O share the same address
  space.

I/O
CPU
Addresses
Instruction Processing Unit
Instructions
Control
Arithmetic Logic Unit
Memory
Data
3
Instruction Set Architecture

• Neumann ISA had only 21 instructions.
• Some authors considered it an early RISC
  architecture.
• Three components of the instruction set are
  Address, Data Types and Operations.
• Addresses
• Organization of Memory, how operands are
  referenced and results stored.
• Only two random access memories (RAM),
  accumulator and main memory.
• No modifications to the address such as register
  relative or indexing.
• Local storage is a single accumulator.

Memory
ALU
Accumulator
4
Instruction Set Architecture Data Types

• Fractions
• A 40 bit word types as a 2s complement fraction.

0
39
Fraction

• Instructions
• Memory organized in 4096 words (212).
• Two 20 bit instructions are allocated to the
  40bit memory word.
• An 8-bit operation code.
• A 12 bit address.

39
28
27
20
19
0
8
7
Left Address Left Op-Code Right
Address Op-Code
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Instruction Set Architecture - Registers

• Has seven registers for interpreting instructions
  from memory.
• No I/O shown

ALU
Control
Accumulator
IBR
IR
Program Counter
MQ
Memory
MAR
MDR
ALU Arithmetic Logic Unit. IR Instruction
Register IBR Instruction Buffer Register MAR
Memory Address Register MDR Memory Data
Register MQ Multiplier Quotient Reg.
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Instruction Set Architecture - Operations

• Three types Move, ALU and Control
• Move moves data between the accumulator,
  multiplier quotient register (MQ) and memory
• ALU operations such as add, subtract, multiply
  and divide
• Control Unconditional and Conditional branch
  instructions that redirect program flow.

ALU Arithmetic Logic Unit. IR Instruction
Register IBR Instruction Buffer Register MAR
Memory Address Register MDR Memory Data
Register MQ Multiplier Quotient Reg.
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Registers
Arithmetic of Data Process Registers
Memory Interface Registers
Memory Instructions Data
Address
From PC
Memory
MAR
From IR(data)
ALU Control
MAR LOAD
ALU
MDR
To Acc
ACC LOAD
To IR
Accumulator
Data
CLEAR
MDR LOAD
Control Registers
Address Bus
From MDR
Memory Instructions
PC Inst. address
PC
PC LOAD
UPCOUNT
Data ADDRESS
OP
IR
IR LOAD
Data Bus
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Instruction Interpretation Cycle
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Instruction Execution Cycle - 68HC11 Example
Instruction Memory Loc.
Machine Code LDAA 2000
C000 B6 20 00

• Instruction Execution Cycle (68HC11).
• PC set to C000. Content of the memory locations
  at 2000 is 37.
• A read cycle (or sequence of read cycles) to
  fetch instruction opcode and addressing
  information.
• It performs a read cycle to fetch the memory
  operands.
• It performs the operation specified by the opcode
• It writes back the result to either register or
  memory location.

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Instruction Execution Cycle - HC11 Example (cont.)
Instruction Memory Loc.
Machine Code
LDAA 2000 C000
B6 20 00

• Steps
• Value of PC is placed on the address bus with a
  request to read the contents of that location.
• 8 bit value at C000 is the instruction opcode
  (B6). Is placed on the DB by the memory and
  retuned to the processor where the control unit
  interprets the instruction. PC incremented by 1
  pointing to C001.
• The control unit recognizes the LOAD instruction
  needs a 2 byte value for the operand address
  located in the next two memory locations. Two
  read instructions follow and PC incremented by 2.
  PCC003 and address2000 stored in a internal
  register.
• LOAD requires an additional read cycle. 2000 is
  placed on the address bus with a read request.
  Contents of 2000 is place on the data bus and
  stored in ACC A.

Address Bus
C000
CPU
B6
Data Bus
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Limitations of the von Neumann ISA

• No automatic address modification
• The address in the instructions must be modified
  by other instructions to index through an array.
  This is the self-modifying code that is very
  prone to programming error.
• No base register mode
• The program counter is an implemented register
• All modern processors have an architected PC