ASI practical work what to do

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ASI practical work - what to do?

• Best solution
• full ASIC design, manufacture and test
• expensive!
• fabrication takes too long
• Usual solution
• full design, simulation only or analogue
  field-programmable device
• cheap!
• yet another keyboard-only exercise
• demotivating?
• works too well??

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ASI practical work - what to do?

• Our solution
• make a teaching chip containing many individual
  transistors and small subcircuits, all pinned-out
• have students characterise these blocks and
  connect them at pins to make up larger circuit
  blocks
• moderate, one-off, cost
• real problems arise immediately, and real
  solutions must be found
• Chip constraints
• 0.35?m N-well AMS CMOS process
• 100 pins, 3mm?3mm

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ASI Chip Floorplan
Outer IO ring
Inner IO ring
1
2
17
16
15
3
4
Inner IO ring
Inner IO ring
14
Outer IO ring
Outer IO ring
5
18b
6
18a
7
13
20
11
12
8
9
10
Inner IO ring
19
Outer IO ring
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ASI chip ground rules

• Large(ish) transistors
• normally Lmin 1?m, Wmin 10?m
• some minimum L devices for characterisation
• Bias currents for W 40?m around 100?A
• Node capacitances assumed to be 5pF/pad 5pF
• accept that frequency responses will be very poor
• All transistors/structures available NMOS and
  PMOS
• 5V power supply - compatibility with equipment

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ASI chip contents

• NMOS and PMOS current mirrors with array of
  devices of different widths
• NMOS and PMOS current mirrors with array of
  devices of different lengths
• Floating NMOS and PMOS devices
• Three different op-amps
• Ring Oscillator

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ASI chip contents

• Inverter with transistors laid out sideways
• Switched current mirror laid out to make DAC
• Additional circuitry required to make a bandgap
  reference
• R and 2R resistors of different types
• C and 2C capacitors of different types

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What can we do with the ASI chip?

• Transistor matching
• matching for different width
• matching for different lengths
• short-channel effects
• Current source/sink output impedance
• Cascode current source/sink output impedance
• Source followers

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What can we do with the ASI chip?

• Basic amplifiers
• resistive load
• active load
• current-source load
• push-pull amplifiers
• Cascoded amplifiers
• Differential stages
• with different loads
• cascoded
• folded cascode

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What can we do with the ASI chip?

• Two-stage amplifiers
• compensation
• output impedance
• Simple three-stage amplifiers
• op-amps
• Simple DAC
• Bandgap reference
• Other things yet to be found !!

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ASI chip

• Transistors are present on the chip such that all
  the circuits can be made invertedNMOS ?PMOS
• PMOS sized to give same ?
• Chip contains a simple OTA, a 3-stage externally
  Miller compensated op-amp and a folded cascode
• OTA is made from same-sized transistors as can be
  made up from separate bits

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The PCB
DC level
AC Signal conditioner
DACswitches
5V
GND
offset
BNC ACinput
ThreeDCcurrentsource/sinks
ASIC1
FourDCvoltagesources
ASIC2
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The PCB

• The PCB carries and protects the chip
• One 0?5V power supply
• protected against polarity inversion and
  over-voltage
• One AC connection from signal generator
• processed by internal op-amps
• cannot go outside 0?5V range
• AC available inverted and non-inverted
• DC platform provided, and small DC offset
• All gate connections have Schottky to GND and VDD
• Resistors in series with all gate connections

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The PCB

• Four voltage sources available
• Three (floating) current sources available
• All connections by wire-wrap
• Gives very reliable, easily changed, connections
• Multiple connections to one point possible
• Low resistance, low capacitance, point-to-point
• Cheap!
• Takes up little space on board

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Simulations

• We have 60 Cadence licences available
• In lab we have PCs
• they run Windows or Linux
• we can connect to SUNs running Cadence from
  either
• Simulation is a key part of exercise
• Must be able to run simulations and do
  practicalwork at the same bench
• Feed measured results into simulation and compare
• Adjust simulations to match measured results -
  refine model

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Transistor Characterisation
NMOS characterisation lines simulations,
points measurements
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Transistor Characterisation

• Very poor match indeed
• However, when you realise that the model isnot
  this

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Experience so far

• Almost all students who may enrol have enrolled -
  42 students on course
• Students very enthusiastic
• no absences from lab or lecture
• students doing lab work and simulations intheir
  own time
• comments like Ive learned more here than in the
  previous three years! (I hope this is an
  exaggeration!)

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Experience so far

• The chip has survived!
• The chip, basically, works (so far as it has been
  tested)
• Use of wire-wrap has caused no problems
• Bugs have proved very useful
• Wiring has been made too thin
• Meters are not good enough
• Note, however, only done DC stuff so far - there
  will be more bugs with AC and high gain

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Problems

• This has been very expensive!!
• Chip costs met by SE (grateful thanks!)
• Cost of PCBs
• Cost of components - much higher than expected
• Cost of assembly - many man-days
• Cost of extra equipment, e.g. ?A meters
• Huge investment of academic staff time, vastly
  more than expected
• On the positive side, recurrent costs should not
  be specially high

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Outcome so far

• Considerable increase in student enthusiasm
• Students very engaged with material
• Considerable increase in student knowledge of
  analogue, even at this stage
• Increase in students background knowledge
• Staff learning and having fun too!
• But beware - you need really knowledgeable staff
  with a wide background of practical work
• Overall this has been a very, very positive
  exercise