CSE-308 Digital System Design (DSD)

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CSE-308 Digital System Design (DSD)
N-W.F.P. University of Engineering Technology,
Peshawar
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Dataflow Modeling

• Expressions, operands and operators form the
  basis of dataflow modeling.

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Verilog Operators

• Arithmetic , , , /,
• Binary bitwise , , , ,
• Unary reduction , , , , ,
• Logical !, , , , , !, !
• returns x if any of the input bits is x or z
• compares xs and zs
• Relational lt. gt, lt, gt
• Logical shift gtgt, ltlt
• Conditional ?
• Concatenation

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Arithmetic Operators
Operation performed Operator Symbol Operator Type
Arithmetic Multiply
Arithmetic / Divide
Arithmetic Add
Arithmetic - Subtract
Arithmetic Modulus
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Logical Operators
Operation performed Operator Symbol Operator Type
Logical AND
Logical OR
Logical ! NOT
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Conditional Operators
Operation performed Operator Symbol Operator Type
Conditional ? Conditional
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Concatenation and Replication Operators
Operation performed Operator Symbol Operator Type
Concatenation Concatenation
Replication Replication
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Example Concatenation operator
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Replication Operator!

• A 2b01
• B 4 A // 01010101
• Thus B 01010101

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Relational Operators
Operation performed Operator Symbol Operator Type
Shift gtgt Right Shift
Shift ltlt Left Shift
Relational gt Greater than
Relational lt Less than
Relational gt Greater than or equal
Relational lt Less than or equal
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Reduction Operators
Operation performed Operator Symbol Operator Type
Reduction Reduction and
Reduction Reduction nand
Reduction Reduction or
Reduction Reduction nor
Reduction Reduction xor
Reduction or Reduction xnor
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Bitwise Arithmetic Operators
Operation performed Operator Symbol Operator Type
Bitwise Bitwise negation
Bitwise Bitwise and
Bitwise Bitwise Or
Bitwise Bitwise XOR
Bitwise or Bitwise XNOR
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Equality Operators
Operation performed Operator Symbol Operator Type
Equality Equality
Equality ! Inequality
Equality Case Equality
Equality ! Case Inequality
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Data Flow Modeling Continuous Assignment

• Continually drive wire variables
• Used to model combinational logic or make
  connections between wires
• module adder_4 (a, b, ci, s, co)
• input 30 a, b
• input ci
• output 30 s
• output co
• assign co, s a b ci
• endmodule

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• module mux2_1(in1, in2, sel, out)
• input in1, in2, sel
• output out
• assign out sel ? in2 in1
• endmodule

module stimulus reg IN1, IN2, SEL wire
OUT mux2_1 MUX(IN1, IN2, SEL, OUT) initial begin
IN1 1 IN2 0 SEL 0 5 SEL 1 5 IN1
0 end initial monitor(time, " IN1b,
IN2b, SELb, OUTb\n", IN1, IN2, SEL,
OUT) endmodule