DATA%20ACQUISITION%20SYSTEM

1
DATA ACQUISITION SYSTEM
16K X 16 DUAL PORT RAM
RADAR INTERFACE
IDE INTERFACE
36
36
25
25
FPGA2 APEX20K200E
FPGA1 APEX20K200E
BUFFER
BUFFER
30
ATA 66
30
I Channel
AD6640 (65 MSPS)
2
12
Analog /- 1V
BUFFER
ATA 66
30
30
AD6640 (65 MSPS)
12
Analog /- 1V
Q - Channel
60
10/100 Mbps Ethernet
ETHERNET PHY
RJ45
SAMSUNG MICROCONTROLLER ARM - RISC CORE (50MHZ
32 BIT, 8 KByte SRAM)
BOOT FLASH 512K X 16 PROGRAM MEMORY
SDRAM 2 X 1M X 16 DATA MEMORY
JTAG PORT
RS232 DRIVER
SERIAL PORT
2
FPGA2 ARCHITECTURE
From DPRAM (16K x 16)
IDE CHANNEL 0
DPRAM / DMA CONTROLLER
WRITE FIFO
UDMA MODULE
IDE FSM
READ FIFO
TO HARD DISK
PIO MODULE
256 X 16
256 X 16
WRITE FIFO
UDMA MODULE
IDE FSM
REGISTER BANK
READ FIFO
TO HARD DISK
PIO MODULE
PROCESSOR INTERFACE
256 X 16
IDE CHANNEL 1
UDMA Ultra DMA PIO Programmed
Input/Output FSM Finite State Machine
Processor Interface
3
DEVELOPMENT OF AN ULTRA DMA MODULE FOR A HARD
DISK CONTROLLER

1. Specifications IDE ATA5 Standards
2. RTL Description of Ultra DMA (Direct Memory
   Access) Module in Verilog HDL (Implementation of
   UltraDMA Modes 0 to 4)
3. Behavioral description of the Hard Disk Interface
4. Functional and Timing Simulations using VerilogXL