Status of SPD electronics Very Front End

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Status of SPD electronicsVery Front End

• Review of ASIC runs
• Whats new RUN 4 and 5
• Next Actions

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SPD VFE ASIC Architecture
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Review of ASIC runs

• RUN1 (Sep 2000)
• Test separate blocs
• 1 full channel
• RUN2 (June 2001 test beam)
• 4 full channels
• test ECL vs CMOS output
• RUN 3 (Jan 2002)
• New tunnable subtractor
• 1 full channel with digital control
• On-chip DAC to program thresholds
• RUN 4 (May 2002)

TESTED
TESTED
Under TEST
In FAB
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Features

• 0.8 ?m AMS BiCMOS Technology
• Processing speed 40 MHz
• Analog Processing Digital Control
• Dual channel
• Fully differential
• SEU and SEL protection for digital logic
• Triple voting (custom output stage in FF)
• Guard rings
• Power consumption lt 2 W / 64 channels
• Signal range. 0 to 5 MIP
• Electronics resolution 5 of 1 MIP
• Dynamic range 40 dB (7 bits)

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Run 2
Sept 2001 4 full channels test ECL vs CMOS
output Pile-Up compensation fixed at 17
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Run 2 Experimental Results (I)
Offset (Output Zero Error)
38.6 mV ?io 70 mV r.m.s.
Gain
16.51 (for a typical input pulse) ?io 0.091
r.m.s.
T reset
5.5 ns (for 1 V output)
Noise
about 1 mV r.m.s
Output range
gt?1V for an arbitrary input signal
Linearity error
lt 0.5 full scale
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Run 2 Experimental Results (II)

• Discriminator internal signals for a typ. pulse
• Interleaved operation of the 2 subchannels

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Run 3
January 2002 1 full channel with digital
control New tunnable subtractor On-chip Digital
to Analog Converter to program thresholds
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Run 3
7 bits pseudo-differential DAC 1b for sign 6b for
modulus R-2R architecture
DAC transfer function 3 different ref voltages
INL 3 different ref voltages
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PMT DC current problem
PMT supports only 100 uA DC (18 uA with present
base) SPD at hottest point (10 occupancy)
64 channels 1pC / MIP 0.1 / 25 ns 250 uA

• Solution
• Build a new base supporting 100 uA
• Reduce PMT gain (100 fC / MIP).
• Increase PMT load Resistor (150? ? 400?)
• Increase ASIC gain (factor 3)
• Decrease threshold for 1 MIP by a factor 2.

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RUN 4

• Sent 24-05-2002
• Complete processing channel with digital control.
• Separate analog blocks digital ctrl
• Works at 3.3 V to reduce power consumption. All
  blocks have been resdesigned at transistor level
• The previous power consumption per chip was 1.2
  W, now it will be around 600 mW.
• Higher gain (x3) to meet PMT DC current limit
  requirements. A fully differential preamplifier
  is added before the integration stage.
• Towards final prototype
• Will be tested Sep-Oct 2002

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Front End Amplifier

• Differential input. common mode interference is
  cancelled
• Offset compensation is possible using external
  resistors.
• High Bandwidth (gt 200MHz).
• Low gain (?6).
• Low impedance output (independent integration
  switch).
• Layout optimised for matching input transistors
  and resistors and current sources.

70 mV r.m.s. (15 samples)
Offset (output)
??
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Front End Amplifier
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Modified Track Hold
DAC
TRANSCONDUCTOR
0 lt ? lt 1/2
GUGGENB TRANSCONDUCTOR
OUTPUT STAGE
Integ
Comp
TRANSCONDUCTOR
Differential Signal
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DAC
TRANSCONDUCTOR
OUTPUT
GUGGENB
Integ
Comp
TRANSCONDUCTOR
STAGE
TRANSCONDUCTOR
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poly2
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• RUN 5
• Design Completed
• Area 30 mm2
• 8 full channels digital ctrl
• Works at 3.3 V to reduce
• power consumption
• Higher gain to meet
• PMT current limit
• requirements.