IC Layout Techniques

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IC Layout Techniques
Saravanan Ramamoorthy
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N Well
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• Source and Drain

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• Gate or poly

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• Metal 1 Contact

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DRC

• (Design Rule Check)

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• RX Active region ( gate oxide and N-/P
  diffusion region )
• NW N-Well region
• PC Polysilicon line (gate of the
  transistor)
• BP Area which are blocked from P
  source and drain implant
• CA Square stud contact which contacts
  either RX or PC to M1
• M1 First level thin metal layer
• V1 Square vias for connecting M1 to M2
  

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• Minimum length and width of CA should be 0.2um

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• Minimum overlap of CA by M1 should be
  0.02um

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• Min overlap of CA by RX should be 0.1um

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• Min distance between CA should be 0.24um

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• Min distance between CA and PC should be 0.16um

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• Min PC width should be 0.18um

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• Min distance between PC should be 0.24um

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• Min distance from RX to PC and BP should be
  0.24um and 0.36um respectively

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• Min overlap of RX by N well should be 0.42um

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• Min distance between RX should be 0.26um

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• Min M1 width should be 0.24um

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• Min distance between M1 should be 0.2um

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• Min length and width for V1 should be 0.28um

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• Min M2 width should be 0.28um