Loop Optimizations

1
Loop Optimizations

• Neeraj Kr. Singh
• csa02030_at_cse.iitd.ac.in

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Outline

• Loop Optimizations-why?
• Loop Optimizations in Compilers Context
• Loop Optimizations in HLS Context

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Loop optimization-why?

• Execute a number of times
• Takes most of the time

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Illustration

• for(I0Ilt20I)
• A105
• / Rest of the code doesnt modify A/

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Loop Optimizations in compiler context

• Induction Variables and Cost Reduction
• Loop Invariant Code Detection and Motion
• Loop Fusion
• Loop Fission
• Loop Unrolling

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Induction Variables and Cost Reduction

• For(I0Ilt20I)
• T4I
• / Rest of the code doesnt modify T/

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Induction

• For(I0Ilt20I)
• TT4
• / Rest of the code doesnt modify T/

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Loop Invariant Code

• For(I0IltT-2I)
• / The code doesnt modify T/

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Loop

• T1T-2
• For(I0IltT1I)
• / The code doesnt modify T/

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Loop Fusion

• For(I0Ilt20I)
• AII
• For(I0Ilt20I)
• BI2I

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Loop

• For(I0Ilt20I)
• AII
• BI2I

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Implication of Loop Fusion

• A number of unnecessary tests and increments were
  saved.

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Loop Fission

• For(I0Ilt20I)
• AII
• BI2I

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Loop

• For(I0Ilt20I)
• AII
• For(I0Ilt20I)
• BI2I

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Motivation for Loop Fission

• Cache Memory

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Loop unrolling

• For(I0Ilt20I)
• AII

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Loop unrolling

• For(I0Ilt20I4)
• AII
• AI1I1
• AI2I2
• AI3I3

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Loop Unrolling-Types

• Partial
• Full

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Partial Loop unrolling

• For(I0Ilt20I)
• AII

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Partial Loop Unrolling

• For(I0Ilt20I4)
• AII
• AI1I1
• AI2I2
• AI3I3

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Advantages

• Number of tests are reduced
• Parallelism

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Disadvantages

• Cache

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Full Loop unrolling

• For(I0Ilt8I)
• AII

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Full Loop Unrolling

• A00
• A11
• A22
• A33
• A44
• A55
• A66
• A77

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Advantages

• No tests
• Parallelism
• No cache problem
• For array references, addresses may be calculated
  beforehand.

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Loop Optimizations in HLS Context

• Loop Unrolling
• Induction Variables and Cost Reduction
• Loop Invariant Code Detection and Motion
• Loop Fission
• Loop Fusion

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Loop Unrolling

• For(I0Ilt8I)
• AII

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Loop

• Adder takes 3 ns
• Clock time is 30 ns
• We have 8 adders

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Loop

• A00
• A11
• A22
• A33
• A44
• A55
• A66
• A77

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Loop

• All the stuff can be done in one clock cycle as
  compared to 8 clock cycles in rolled one.

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Arrays in HLS

• Can be mapped to memory or a sequence of wires
• Depends on the designer

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Arrays mapped to wires

• A be an Array of 8 elements
• Array Access
• tmpAI

A_0
tmp
A_7
I
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Arrays

• Non Constant Array Index Assignment
• AItmp

A_7
A_7
Decoder
A_0
A_0
tmp
I
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Full Unrolling and Arrays

• No hardware is further required for array
  indexing as the Array indices are constant.

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Loop Unrolling in HLS- Epitome

• Loop
• For(I0Ilt8I)
• tmptmpAI
• Unlimited Resources
• Clock Period is Long Enough to Schedule 5
  operations(incrementcomparisonadd)

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Loop

• Rolled
• Schedule1 addition,comparison and increment per
  cycle.
• Resources 1 adder, 1 comparator, 1 incrementer,
  indexing logic.
• Latency 8 clock cycles

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Loop

• Fully Unrolled
• Schedule4 additions per clock
• Resources 4 Adders
• Latency 2 clock cycles

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Loop

• Partially Unrolled- 2 times
• Schedule2 additions, 2 increments,1 comparison
  per clock.
• Resources 2 adders, 1 comparator, 2 increments
• Latency 4 clock cycle

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References

• Elliott John P.,Understanding Behavioral
  Synthesis- A Practical Guide to High-Level
  Design.
• Aho Alfred V., Sethi Ravi, Ullman Jeffrey D.,
  Compilers- Principle, Techniques and Tools.

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Questions?

• Thanks.