[15-213 S04] Recitation: 02/23/04 - PowerPoint PPT Presentation

About This Presentation
Title:

[15-213 S04] Recitation: 02/23/04

Description:

Exam1. Feb 26, Thursday. Exam1 Review. Today! 7 - 9 pm in Wean 7500. Lab 4. More thinking then coding ... a memory location that is referenced once is likely to ... – PowerPoint PPT presentation

Number of Views:20
Avg rating:3.0/5.0
Slides: 22
Provided by: Anu78
Learn more at: http://www.cs.cmu.edu
Category:
Tags: exam1 | recitation | s04

less

Transcript and Presenter's Notes

Title: [15-213 S04] Recitation: 02/23/04


1
15-213 S04 Recitation 02/23/04
  • Cache Locality
  • Reminder
  • Exam1
  • Feb 26, Thursday
  • Exam1 Review
  • Today! 7 - 9 pm in Wean 7500.
  • Lab 4
  • More thinking then coding
  • Due next Thursday (March 4)

2
Locality
  • Temporal locality
  • a memory location that is referenced once is
    likely to be reference again multiple times in
    the near future
  • Spatial locality
  • if a memory location is referenced once, then the
    program is likely to reference a nearby memory
    location in the near future

3
Practice Problem 6.4
  • Permute the loops so that it scans the
    3-dimensional array a with a stride-1 reference
    pattern

int summary3d(int aNNN) int i, j, k,
sum 0 for (i 0 i lt N i)
for (j 0 j lt N j ) for (k
0 k lt N k ) sum
akij
return sum
4
Array Organization in Memory
a000, a001, , a00N-1,
a010, a011, , a01N-1,
a020, a021, , a02N,
a100, a101, , a10N,
aN-1N-10,aN-1N-11,,aN-1N-1N-
1
5
Solution
int summary3d(int aNNN) int i, j, k,
sum 0 for (k 0 k lt N k)
for (i 0 i lt N i ) for (j
0 j lt N j ) sum
akij
return sum
6
Cache Access Patterns
  • Now its your turn to spend 15 minutes working on
    Practice Problems 6.15-6.17 ?
  • Handout is a photocopy from the text book
  • Note that
  • sizeof(struct algae_position) 8
  • Each cache block (16 bytes) holds two
    algae_position structs
  • The 1616 array requires 2048 bytes of memory,
    twice the size of the 1024 byte cache

7
Direct-mapped Data Cache
  • Each row 16 struct items, 8 cache blocks, 128
    bytes
  • Each column 16 struct items
  • Yellow area 1024 bytes, green area 1024 bytes

8
6.15 Row Major Access Pattern
9
6.15 Stride of two words
  • First loop, accessing all xs
  • When a cache miss happens, load a block from
    memory

10
6.15 Stride of two words
  • First loop, accessing all xs
  • When a cache miss happens, load a block from
    memory

11
6.15 Stride of two words
  • Second loop, accessing all ys
  • Same missing pattern, the green area flushes
    blocks from the yellow area

12
6.15 Stride of two words
  • Second loop, accessing all ys
  • Same missing pattern, the green area flushes
    blocks from the yellow area

13
Answer to Problem 6.15
  • A 512
  • 16x16 256 array elements in total
  • twice for each element
  • B 256
  • every other array element experiences a miss
  • C 50

14
6.16 Column Major Access Pattern
  • New access removes first cache line contents
    before it is used

15
6.16 Column Major Access Pattern
  • New access removes first cache line contents
    before it is used

16
Answer to Problem 6.16
  • A 512
  • B 256
  • C 50

17
6.16 Column Major Access Pattern
  • What if the cache was 2048 bytes?
  • No misses on second access to each block, since
    the entire array fits in the cache

18
Answer to Problem 6.16
  • A 512
  • B 256
  • C 50
  • D 25

19
6.17 Stride of One Word
  • Access both x and y in row major order

20
6.17 Stride of One Word
  • Access both x and y in row major order

21
Answer to Problem 6.17
  • A 512
  • B 128
  • All are compulsory misses
  • C 25
  • D 25
  • Cache size doesnt matter since all misses are a
    MUST
  • The block size does matter though
Write a Comment
User Comments (0)
About PowerShow.com