ADC Analyzer Version 3'2'1

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ECE 191 Fall 2003Performance Enhancement of
Analog to Digital converter through Dithering
Sponsor The Titan Corporation
Scott Marks -RF Engineering Manager
Professor Dr. Pankaj Das Dr.
Charles Tu
National Security Solutions
Group 8 Members Chen-Hua Yang Cheng-Han
Wang Chi-man Cho Hung William Chan
Szu-Chun Tsao
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Week 5 Agenda

• Hardware AD6645 ( Tested )
• FIFO Board ( Tested )
• Software ADC Analyzer Software ( Tested )
• Modeling Non-Ideal components
• Noise Diode 2 to 3 weeks
• Band Pass Filter 2 to 3 weeks

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Gantt Chart
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Hardware Layout
High speed ADC FIFO Evaluation kit
Clock Oscillator, MX045, 80MHz
Power Connector
Signal Input
IDT72V283 32K FIFO (ADC input Channel)
AD6645
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Hardware Set up

• An misleading adapter delayed our experiment.
• The limitation of the existing signal generator
  is 15Mhz signal. However, we need 4080Mhz RF
  signal. We will share the RF Signal generator
  with another graduate student.
• We will use the band pass filter to examine more
  specific frequency range.

Computer Spectrum Analysis
RF signal
ADC
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ADC Analyzer Configuration

• Choose AD6645 as Device
• 14 Bits
• Device Temperature 25o C

• Channel A only
• Sample at 21416384
• Everything else use Default setting

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RF Generator V.S. Function Generator

• Less Harmonic terms appears
• Better Noise Floor (less dB)
• Higher Fundamental Signal
• Higher Frequency

Function Generator at 15Mhz (Max)
RF Generator at 15Mhz (up to 1Ghz)
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ADC Spectrum Analyzer
What can we get out of this chart

• Analog Signal Frequency
• Signal to Noise Ratio
• Fund. Frequency amplitude
• 2nd to 6th Harmonic terms
• Noise Floor

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Predicted Result with Dither Signal
Noise to Signal and Distortion ratio will
increase !!
Harmonic terms will be reduced
Noise floor will raise
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More Non-Ideal Modeling

• Sample and Hold
• Insufficient Bandwidth
• Attenuated Amplitude
• Low resolution
• Clock Jittering during S/H
• Treated as Some kind of Noise (Phase noise)
• Pre-ADC
• DNL
• Discussed
• Imperfect Voltage Divider
• Distortion (Nonlinearity)

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Sample and Hold

• Sufficient Bandwidth

• Insufficient Bandwidth

0.1 Settling time Requirement.
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Sample and Hold

• Insufficient Bandwidth
• It seems not to introduce Non-Linearity
• Reduce resolution
• Unable to reach the destination level in time
• Other Non-ideal condition
• Clock feed-through
• Switch Non-Linearity

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Clock Jittering during S/H

• What is Jitter ?
• Clock with jitter means the moment of
• sampling in a cycle varying within a
  certain T_rms.

Signal w/o jitter
jitter
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Clock Jittering during S/H

• SNR, SFDR are getting worse when T_rms is getting
  larger.

SNR SFDR
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Non-Ideal Voltage Divider

• Resistance against Length is not a Ideal-Linear
  function.

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Non-Ideal Voltage Divider

• 2.4 Max Dev from Ideal Line

• 19.5 Max Dev from Ideal Line

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Non-Ideal Voltage Divider
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Narrow Band Dither
Wideband Dither
Narrow Band Dither
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Whats Next

• More model simulation for non-ideal condition
• Ex clock feed-through, finite gain op-amp.
• More detail on dither simulation on Matlab.
• Wait for the noise source ( noise diode )