The Science of Electronics: Analog Devices

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The Science of Electronics Analog Devices
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Chapter Six Large-Signal Transistor Circuits

• Contents
• 6.0 Introduction
• 6.1 The Common-Emitter Amplifier
• 6.2 The Common-collector or Emitter-Follower
  Connection
• 6.3 Two-Transistor Combinations
• 6.4 The FET Switch

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6.0 Introduction

• Classification of transistor circuits
• (1) large-signal circuits
• The variations of voltages and device
  characteristics be considered. currents are
  sufficiently great to require that the full,
  nonlinear
• (2) small-signal circuits
• The signal components of voltages and currents
  are sufficiently small to permit the use of local
  linear models of device behavior.
• The boundary is occasionally fuzzy, and depends
  on the accuracy with which one needs to know or
  predict the operating characteristics of a
  particular circuit. In this chapter. we explore
  circuits of the large-signal variety, admitting
  at the outset that we are willing to sacrifice
  some accuracy in the representation of device
  characteristics in order to carry out a simple
  analysis of circuit performance.

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6.1 The Common-Emitter Amplifier(1)??????
6.1.1 A Graphical Approach
1. Input terminals Operating point
From our discussion in Chapter 9, we know that
between the base and emitter terminals, the
transistor has the v-i characteristic of a
semiconductor diode. Figure (a) below shows a
typical n-p-n silicon transistor input
characteristic illustrating this diode behavior.
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6.1 The Common-Emitter Amplifier(2)
Four input load lines are shown on the input
characteristic, each drawn with slope -1/RS, and
each one intercepting the vBE axis at a different
value of the source voltage. In the example
shown, we have used a value of RS 20 k?. The
four load lines will be used below to trace the
operation of the circuit as if the input voltage
were changing by 0.4 V steps from vs1to vs2 to
vs3 and finally to vs4
The intersection of each load line with the input
characteristic gives the operating point for that
value of input voltage. Thus in our example, the
base current is zero when vS is equal to vs1
(cutoff), and increases to 10?A, 30?A, and
finally to 50?A as vs increases to vs2, vs3, and
vs4.
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6.1 The Common-Emitter Amplifier(3)
2. Output terminals operating point
To find the output operating point corresponding
to each value of vs, we must locate the
intersection of the output load line with the
transistor characteristic corresponding to the
correct value of base current.
Thus, for vs, which yielded iB 0, we find the
intersection between the output load line and the
output characteristic for iB 0. This
intersection occurs at ic and vCEVCC. and
corresponds to the transistor being in cutoff 
for  vs vs1. The remaining three operating
points are found similarly.
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6.1 The Common-Emitter Amplifier(4)

• We note that to turn the transistor on, it is
  necessary to have vs exceed the 0.6 V diode
  threshold  voltage of the base-emitter junction.
  Once this threshold is exceeded, the base current
  increases steadily in response to an increase in
  vs. As the base current increases, the output
  operating point moves up the load line from the
  cutoff characteristic (iB 0) into the
  active-gain region. Eventually, vCE decreases
  until the collector-base junction becomes
  forward-biased, resulting in saturation with a
  small, nearly constant vCE.

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6.1 The Common-Emitter Amplifier(5)
3. Common-Emitter Amplifier Transfer
Characteristic
For vslt 0.6 V, the transistor is cutoff. As vs
increases, vCE drops from its cutoff value of VCC
toward its saturation value of about 1 V. The
slope of the transfer characteristic in
the active-gain region is about -15, and
corresponds to the voltage gain of the amplifier.
That slope is labeled with the notation
-?FRL/RS.  Let's look the circuit simulation
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6.1 The Common-Emitter Amplifier(6)
6.1.2 Large-Signal Model for the Bipolar Junction
Transistor
In the active-gain region of the BJT, B-E
junction is forward bias, which looks like a
diode,  and B-C junction is reverse bias. And the
current of collector, iC, is controlled by the
base current, iB, therefore, a transistor may be
modeled  as (a)
If the forward-bias diode model is used, the
large-signal transistor model is shown as (b)
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6.1 The Common-Emitter Amplifier(7)
Common-emitter amplifier with large-signal model
Substituting the large-signal model for the
transistor in the amplifier, we yield the
common-emitter amplifier with large-signal model
If VBE lt0.6V , the ideal diode is reverse biased
and the transistor is cutoff. If iB gt 0, the
ideal diode is forward biased, becoming a short
circuit, and vBE becomes equal to 0.6 V. Thus for
iB gt 0,
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6.1 The Common-Emitter Amplifier(8)
Using KVL, we find that
Note that the slope is -(?FRL/RS), called voltage
gain. For our example, RL 3 k?, RS 20 k?, and
?F 100 (from the characteristics). This slope
has the value of -15, as estimated in Section
10.1.1 from the graphical analysis.
The validity of above formula is limited to the
active-gain region, which requires vsgt0.6V and
vCEgtVCE, sat. Therefore, the valid range of input
voltage, vS, for active-region operation is
Any larger value of us produces saturation, while
any smaller value produces cutoff.
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6.1 The Common-Emitter Amplifier(9)
10.1 .3 An Example
A transistor switch is used to light the 500O
lamp when vA 1 V. The lamp has a nominal
resistance of 500O and requires a current of 15
mA or more for proper illumination.
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6.1 The Common-Emitter Amplifier(10)
The large-signal equivalent of the transistor
amplifier
For vA0 (lt0.6V), the transistor is cutoff. iB0
and iC0, the lamp is off. For vA1V (gt0.6V), the
base current can be calculated as
Then the collector current or the lamp current is
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6.1 The Common-Emitter Amplifier(11)
The current through the bulb, iC, is larger than
the 15 mA needed to light the lamp. However, we
must be careful to check whether our assumption
about saturation is correct.
It is slightly less than VCE, sat . The
transistor has just barely entered the saturation
region. Therefore, we should revise our
assumption, and analyze the circuit assuming
saturation.
If the transistor is saturated, then the
collector current is given by
which is still greater than the 15 mA required.
Thus the circuit switches between cutoff and
saturation in response to 1 V signal, will light
the lamp.
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6.2 The Common-collector or Emitter-Follower
Connection (1)
The input signal, vs, is connected to the base
and the output signal is from the emitter. If the
transistor is in the active-gain region, the
circuit can be modeled as
Note This model is only valid where vCEgtVCE,sat
and iBgt0.
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6.2 The Common-collector or Emitter-Follower
Connection (2)
The transfer characteristic of the
emitter-follower amplifier
From the large-signal model we can write a KCL 
According to the Ohm's law in resistance RE, we
have
In the input loop we write the KVL equation
Combining the equations, we yield transfer
characteristic of the emitter-follower amplifier
in active-gain region.
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6.2 The Common-collector or Emitter-Follower
Connection (3)
When input voltage is sufficient low, the
transistor will enter cutoff region. In this
case, base current and collector current will be
zero, and then the output voltage maintains
zero. 
When input voltage is sufficient high, the
transistor will enter saturation region. In this
case,  collector current will reach the maximum
value and then the output voltage maintains
maximum. Following figure shows the skeleton of
transfer characteristic.
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6.2 The Common-collector or Emitter-Follower
Connection (4)
The maximum range of input voltage for
active-gain region
1. The minimum allowable input voltage
In the active-gain region, we have
By eliminating v0 ,we obtain the dependence of iB
on vS
To satisfy the condition iBgt0, the input voltage
must be greater than 0.6V
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6.2 The Common-collector or Emitter-Follower
Connection (5)
2. The maximum allowable input voltage
In the boundary between active-gain and
saturation regions, the collector-emitter voltage
maintains a minimum value, saturation voltage
VCE, sat.
Therefore, in order to ensure the transistor in
active-gain region, the input voltage should
satisfy
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6.2 The Common-collector or Emitter-Follower
Connection (6)
The voltage gain of the emitter-follower
From the relation between input voltage and
output voltage
we can calculate the voltage gain
It is less than unity for any combination of RB,
RE, and ßF. In most instances, however, RB is
much less than (1ßF)RE, so that the voltage gain
is very nearly, but not quite, unity. Thus, in an
approximate sense, the output at the emitter
follows the input with unity gain. This is the
origin of the name emitter follower.
Although the emitter follower does not produce
voltage gain, it does produce current gain of
magnitude ßF, and therein lies its usefulness.
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6.2 The Common-collector or Emitter-Follower
Connection (7)
6.2.2 A Transistorized Current Source
Split the input and output sub-circuits of the
transistor.
According our analysis for the emitter-follower,
we find 
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6.2 The Common-collector or Emitter-Follower
Connection (8)
The Output Current
Recall the current distributive relation of the
transistor in active-gain state,
Where, we accept the conditions
Using the Ohm's law we have
The result shows that the output current is
constant and independent of RL. Therefore, the
circuit behaves a current source.  Remember,
above discussion is based on that the transistor
is in active gain region.
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6.2 The Common-collector or Emitter-Follower
Connection (9)
The Load Range for the Current Source
 If RL is too large, however, the transistor will
enter saturation state, and the circuit is no
longer valid current source. 
By KVL, we have
To avoid saturation, the emitter-collector
voltage should satisfy
Therefore, the load resistance must satisfy 
Substituting for iL and v3, we get the peak point
of RL
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6.2 The Common-collector or Emitter-Follower
Connection (10)
Let us give an actual example. Suppose VCC12V,
R1500?, R2R3100? and VBE0.7V, VCE,sat0. In
this case, The value of current source is
Look at the demonstration
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6.2 The Common-collector or Emitter-Follower
Connection (11)
6.2.3 A Regulated DC Power Supply
A DC power supply includes a rectifier and a
regulator, which converts ac voltage (sine wave)
to a stable DC voltage. In Chapter 8 we have
introduced a simple example regulator circuit
using zener diode.  We have noted that if the
load is too heavy, the circuit may work
improperly. Here we will discuss a transistorized
circuit. Let's consider following circuit.
If the output voltage of rectifier is larger than
the zener voltage, the zener diode works in
breakdown state and the voltage between its
terminals is fixed as VZ. Substituting equivalent
model for the zener diode  we can plot an
equivalent of the circuit as the right figure.
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6.2 The Common-collector or Emitter-Follower
Connection (12)
Split the input and output loops of the
transistor and apply the Thévenin equivalent
If  RZltltR1, VT ??VZ and RT ??RZ.  Then the
circuit can be simplified as the right circuit.
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6.2 The Common-collector or Emitter-Follower
Connection (13)
The Output Characteristic
According to our analysis on the
emitter-follower, we write the output voltage
In practical application, (1?F)RLgtgtRZ. So
Which is independent of VCC. The circuit behaves
a DC voltage source.
Now we try to find the Thévenin equivalent of the
"source".
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6.2 The Common-collector or Emitter-Follower
Connection (14)
Based on above equation for output voltage, we
can directly write the open-circuit voltage of
the "source"
Next we let the load is short-circuit, and find
the short-circuit current
Thus the Thévenin resistance can be calculated
Finally, we draw out the Thévenin equivalent of
the "source.
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6.2 The Common-collector or Emitter-Follower
Connection (15)
The Limit of load Resistance
According to KCL, 
To ensure the zener diode working in breakdown
region, following inequalities must be satisfied
From the circuit we can calculate the currents
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6.2 The Common-collector or Emitter-Follower
Connection (16)
Therefore, we have
The allowable range of load resistance is
As a practical case, assume VCC12V, VZ6.2V,
RZ10?, R1510?, IZmin5mA and ?F50. In this
case the regulated output voltage is
vL6.2-0.65.6V. The range for load resistance is
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6.3 Two-Transistor Combinations(1)
6.3.1 The Emitter-Coupled Pair 
1. Circuit structure
(1) Symmetric structure two transistors are
identical RC1RC2 (2) Two inputs
v1 and v2 from bases of two transistors
respectively. (3) Multi-type output vC1 or vC2
or vC1- vC2 (4) Emitter-coupled emitters of two
transistors are connected together. (5)
Current-source bias
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6.3 Two-Transistor Combinations(2)
2. Fundamental relations
(1) KVL
(2) KCL
(3) Characteristic of transistors
(4) Output voltages
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6.3 Two-Transistor Combinations(3)
3. Large-Signal Model
Because of the emitter-coupled structure, the E-B
voltages of two transistors are effected by input
voltages and may not be considered constant
voltages.  We use an exponential diode model to
construct the large-signal model of the
circuit.
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6.3 Two-Transistor Combinations(4)
4. Voltage Transfer Characteristic
According to KVL, we have
Applying this relation to the calculation of
collector current iC1
Considering that aF is very close to unity
practically, we have 
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6.3 Two-Transistor Combinations(5)
Then we conclude the output voltages
vC2
vC1
vC1 vC2
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6.3 Two-Transistor Combinations(6)
5. Limits on Input Voltages
To avoid the transistors entering cutoff, it
should be satisfied that
vBE1gt0.5V and vBE2gt0.5V
In active-gain region,  therefore, the input
voltages should satisfy
This is often called the difference mode
limitation of the inputs.
Look at the circuit demo.
To avoid the transistors entering saturation, 
vC1-v1gt0.2V and vC2-v2gt0.2V
The common mode limitation of the inputs
Let demonstrate the circuit application.
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6.3 Two-Transistor Combinations(7)
6.3.2 Difference-Mode Amplification????
According to our above discussion, the output
voltages depend only on the difference between
two input voltages. For this reason, the
emitter-coupled pair is often called a
differential amplifier?????. The difference
between v1 and v2 constitutes a difference-mode
input signal??????.
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6.3 Two-Transistor Combinations(8)
1. The transfer characteristic
(1) Output from the collector of T1
(2) Output from the collector of T2
Linear-region gain
Linear-region gain
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6.3 Two-Transistor Combinations(9)
(3) Differential output 
Linear-region gain
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6.3 Two-Transistor Combinations(10)
2. The bias current source
The characteristic shows that the linear-region
gain is proportional to the bias current I0. So
the gain of the emitter-coupled pair can be
adjusted over a wide range simply by changing the
bias current. A practical biasing current-source
is constructed as 10.2.2. A circuit for
accomplishing this current-source biasing is
shown as
According to the analysis in 10.2.2, the bias
current can be calculated
As the bias current changes, the transfer
characteristic changes. In fact, linear-region
gain depends on the bias current proportionally.
Because of this dependence of linear-region gain
on bias current, the emitter-coupled pair finds
wide usage in automatic-gain-control (AGC??????)
applications and in modulation circuits.
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6.3 Two-Transistor Combinations(11)
6.3.3 Common-Mode Rejection????
1. Common-Mode Input
We have already commented on the fact that when
v1 and v2  are equal, the bias current divides
equally between the identical transistors T1 and
T2 with the result that the output voltages do
not depend on v1 or v2. Voltages that appear
equally at both inputs are called common-mode
voltages (as distinguished from the
difference-mode voltages of the preceding
section).
2. Common-Mode Rejection
The emitter-coupled pair, and the related circuit
involving FETs, has the property that a
common-mode voltage applied to the inputs
produces no change in output. This remarkable
cancellation of common-mode signals is called
common-mode rejection, Op-amps almost always have
an emitter-coupled pair (or source-coupled pair)
as an input circuit to obtain a large common-mode
rejection.
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6.3 Two-Transistor Combinations(12)
3. Common-mode rejection ratio?????
In actual devices there is always some degree of
imperfection in the match between two
transistors. Therefore, actual devices do not
show the perfect common-mode rejection of our
somewhat idealized model. A measure of the
quality of the rejection of common-mode signals
is called the common-mode rejection ratio,
abbreviated CMRR (or often, simply CMR), which is
defined the ratio of difference-mode gain to
common-mode gain
No dimension
dB (??)
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6.3 Two-Transistor Combinations(13)
6.3.4 Complementary-Symmetry Pairs ??????
1. Complementary Transistors 
One transistor is NPN-type and the other is
PNP-type.
2. Symmetry

1. Symmetrical circuit structure
2. Identical device (transistors) parameters

3. Complementary-Symmetry Amplifier Circuit
4. Operating principle
 (1) When vS0 (no input signal), T1 and T2 are
cutoff, then vL0.
(2) When vSgt0.6V, T1 on and T2 off, then vL
follows vS though T1 (Emitter-Follower).
(3) When vSlt-0.6V, T1 off and T2 on, then vL
follows vS though T2 (Emitter-Follower).
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6.3 Two-Transistor Combinations(14)
5. Crossover distortion????
When -0.6VltvSlt0.6, T1 and T2 all are not ON, then
vL maintains 0 and is independent of vS. This is
called crossover distortion.
6. Waveform example
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6.3 Two-Transistor Combinations(15)
7. Eliminate crossover distortion diode biasing
The reason causing the crossover distortion is
zero-biasing of the transistors. If two
transistors have forward-bias of 0.6V when input
voltage is zero, then the crossover distortion
may be eliminated. Following circuit is an
example.
In the circuit, diodes D1 and D2 are all
forward-bias, there is 0.60.6 voltage between
two bases of transistors, which provided a 0.6V
forward-bias for each transistor. The
crossover-distortion is eliminated.
Note The resistances R1 and R2 are necessary to
ensure two diodes forward-bias and conduct-on,
which are missed in the textbook.
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6.3 Two-Transistor Combinations(16)
8. Eliminate crossover distortion Unity-gain
feedback
A second method illustrates the use of an op-amp
in a feedback loop to compare the output voltage
vL against the input signal vS. 
Remember that the open-loop gain of the op-amp
is enormous. This means that the voltage applied
to the bases of the two transistors from the
op-amp's output terminal will have magnitude
sufficient to turn on either T1 or T2 assoon as
vS and vL differ by asmuch as 0.1mV. Following
is the testing waveform.
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6.3 Two-Transistor Combinations(17)

• 6.3.5 A Comment Understanding Op-Amps
• A typical commercial op-amp consists of an
  emitter-coupled pair (or source-coupled pair) for
  initial amplification followed by one or more
  amplification stages that might be of a variety
  of types (common emitters and emitter-coupled
  pairs being most common). The output stage very
  often consists of a complementary-symmetry pair
  in which a combination of diode biasing and
  feedback is used to eliminate crossover
  distortion. Thus with the circuits we have
  already discussed in hand, it becomes possible to
  understand at least qualitatively many of the
  characteristics of actual op-amps. The
  differential amplification and excellent
  common-mode rejection come from the input
  emitter-coupled pair. The limitations on allowed
  common-mode input voltage arise because various
  transistors in either the input stage or in
  subsequent stages can be driven into saturation
  or cutoff by excessive variation of the input
  voltages. The saturation of the op-amp output
  near the supply voltages arises from the
  saturation of one of the transistors in the
  complementary-symmetry output pair. The nonzero
  bias currents at the input terminals are needed
  as base currents of the input transistors to
  assure active-region operation. The input offset
  voltage and input offset currents arise from
  imperfect matching of the input pair of
  transistors and from biasing imperfections.
  Although we have yet to discuss issues related to
  input and output resistance and issues related to
  op-amp speed and frequency response, with a few
  basic circuit concepts involving transistors,
  many quirks of the "black box" begin to make
  sense.

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6.4 The FET Switch (1) ??????

• The uses of the various kinds of field-effect
  transistors (FET) are in many ways similar to the
  uses of the bipolar junction transistors (BJT).
  For example, the large-signal transfer
  characteristic of a common-source amplifier (take
  an NPN common-emitter amplifier and replace the
  transistor with an enhancement mode N-channel
  FET) will be similar in many ways to the transfer
  characteristic of an NPN common-emitter
  amplifier. There is a cutoff region, an
  active-gain region, and a saturation region, and
  many of the same circuit functions can be
  performed. In several important ways, however,
  FETs are not equivalent to BJTs, and it is these
  features that we wish to emphasize here. 
• First, the FET behaves like an open circuit at
  its gate terminal. The MOSFET has an insulator
  between the gate and channel. while the JFET gate
  is back-biased with respect to the channel (in
  normal operation). As a result, the FET in normal
  operation draws no current (or almost no current)
  from a source network and is therefore extremely
  useful in applications where it is necessary not
  to load down a source network that has a high
  Thevenin resistance.
• Second, the FET output characteristics are rather
  symmetrical about the origin. That is, for small
  signals (vDS ltlt VP) the FET channel looks
  like a pure resistance, with no nonlinearities or
  saturation voltage present. As a result, the FET
  is particularly useful as a low-power
  voltage-controlled switch for low-level signals.
  We shall discuss this application further below,
  in full recognition that we are of necessity
  being very incomplete.

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6.4 The FET Switch (2)
6.4.1 The Need For A Graphical Approach
Unlike the BJT, where we could make an extremely
simple model of the device, in many uses the FET
defies the use of simple models made of ordinary
circuit elements (such as diodes and dependent
current sources). Therefore, one must often use
an algebraic representation of the device
characteristics, or one must be willing to work
with graphical methods from graphical
representations of the device characteristics.
For small values of vDS, the output
characteristics of an FET are just a
voltage-controlled resistor. We change the value
of vDS from a value near zero, at which the slope
of the vDS-iD characteristic is largest, to a
value more negative than VP, at which the vDS-iD
characteristic lies along the  iD 0 axis, the
effective resistance of the channel can be made
to change from some minimum value Ron to some
very large value. Thus, by alternating between
zero gate voltage ( vGS 0) and pinchoff (vGSlt
VP) we can use the channel resistance of the FET
as an "ON-OFF" switch.
Voltage-control Resistance Characteristic of an
N-channel JFET
vGS?RDS?vDS /?iD (slope)
vGS0?Ronlt RDS lt8? vGSltVP (pinch off)
50
6.4 The FET Switch (3)
6.4.2 A Simple FET Chopper???
(1) Assumptions
vAltltVPRLgtgtRAgtgtRonvGSvG (because
vLltltVP)
(2) When vG0, FET is ON, then vL vA
(3) When vGVP, FET is pinched off, then vL0
The right figure is a typical operating waveform.
A controlling negative-going square wave is
applied to the gate while a signal is present
from vA, the output waveform will be a chopped or
sampled version of vA.
51
6.4 The FET Switch (4)
The connection for the gate  (1) Gate to Ground
Because of the high input resistance of FET, an
inductive voltage in the gate may be  serious.
Therefore,  in order to ensure zero voltage level
in gate when no control signal provided, there
must be a resistance path between gate and
ground.   (2) Controlling signal The drive
signal may be a square waveform, which amplitude
A. We may apply a diode limiter circuit (8.4.3)
to eliminate the positive part of the drive
signal.
In the circuit, to ensure that the "switch" is
off effectively, the amplitude A of the drive
signal should be greater than VP. 
52
6.4 The FET Switch (5)

• The application of Chopper
• (1) Chopper amplifier????? Very low frequency
  signal to be amplified, which may not be
  amplified using a normal amplifier, is chopped as
  a high frequency pulse firstly. Then the high
  frequency pulse is amplified. Finally, the
  amplified pulse is filtered to restore low
  frequency signal (amplified).
• (2) Time-division multiplexing communication?????
  ?In the communication channel, there are several
  signals to be communicated. All signals are
  chopped and occupies individual time
  respectively. Therefore, the channel is 
  time-shared to each signal. 

53
6.4 The FET Switch (6)
6.4.3 A Two-Channel Analog Multiplexer?????(??)?
A two-channel analog multiplexer selects
alternate samples of two low-level source
waveforms, vA and vB to appear at the output node
vM. The equal but opposite gate drives for the
two FETs are derived from a sine wave, using a
comparator (to produce a large-amplitude square
wave) and an inverter (to produce a square wave
of opposite sign). The gate drive waveforms are
applied through the diode-referral resistor
networks to insure that vGS is zero during the ON
cycle, and not some positive voltage that would
inject carriers into the channel and produce a
signal error. 
54
6.4 The FET Switch (7)
A de-multiplexer ??????? accepts the waveform vM,
and applies the waveform to two alternately
switched sample-and-hold networks??????, one for
vA the other for vB. The drive waveforms for the
de-multiplexer must be accurately synchronized ??
with the multiplexer drives vGA and vGB, or else
the alternate multiplexed samples of vA and vB
will not get switched to the correct
sample-and-hold network at the correct time.
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Chapter Six Physical Electronics Of Transistors
End of Chapter Six