FE Electronics - Overview

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FE Electronics - Overview
U.Uwer
Electronics Review, April 22, 2004
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LHCb Outer Tracker

• Straw Tube Drift Chamber
• 5mm diameter straw tubes, single straw
  tube length 2.5m
• ArCO2 / ArCO2CF4
• max. drift times 44ns
• max. occupancy 7 (MC study)
• 56k channels

• L0 Requirements
• Max. L0 trigger rate is 1.1 MHz
• Max. readout time /event is 900 ns
• L0 buffer with 160 events (4.0 ?s)

264 Module
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Straw Module
5mm
64 Straws
X 2
64 Straws
Cathode
Grounding tongues
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Module Interface to FE Electronics
Feed-through board defines ground ref.
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FE Electronics
tot. dose lt 10krad
FE Box
ASDBLR
Module End 128 channels 16 ASDBLR chips
4 OTIS TDC chips 1 optical link 1.6 Gbit/s
Outer Tracker ST13 56000 channels 432
optical links
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GOL/Aux Board
X 1

• Front-end cards
• have to fit inside the closed shielded FE box
  25 x 30 x 4 cm
• excellent ground connection to straw-tubes and
  module reference ground
• power dissipation of cards is about 25 W / box
  ? water cooling
• easy access should be maintained

TDC boards
X 2
ASD boards
X 8
HV boards
X 4
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HV Board

• 32 channels / board
• Compact capacitors
• Operation in air
• casting/embedding of caps

Capacitors JOHANSON 302R29W331KV4E Max. Volt.
4kV Size 4.6 x 2 x 1.5 mm3
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• TDC board
• radiation hard OTIS TDC chip
• provides bias voltage for ASD
• power rooting for ASDBLR card
• test pulses for ASDBLR

ASD board ASDBLR Chip ATLAS DMILL version
joined ATLAS chip order 28 wafers à1042 chips
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OTIS TDC Chip

• Components
• 32 maskable channels
• DLL, HitRegister, PrePipeline
• 6 bit drift time encoding
• playback data feed-in (testing)
• Pipeline, Derandomizing Buffer
• buffer length 160 evts ? 4.0 µs
• Control Algorithm
• 2 read-out modes 1, 2, 3 BX/evt
• I2C Slow Control Interface
• Programming, ASD bias setting
• DAC ASD-Chip bias

• Status
• OTIS 1.0 in 2002
• Chip Review in June 2003
• OTIS 1.1 received in Feb 2004
• Submission of OTIS 1.2 in May (final chip)

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GOL Auxiliary Board

• Connected to 4 OTIS boards
• Deserialization of OTIS data using CERN GOL
  serializer chip
• Electrical / optical connections to front-end
  electronics
• Optical data link
• Low voltage connections
• Slow-Control connections
• Fast-control (TFC) connection
• Voltage (power) regulation

Testing optical data transmission, development of
readout test system
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FE Electronics Box
Mounting against water cooled plate
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FE Electronics Box
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Services and Distribution Boxes
Low / High Voltage supplies, L1 Buffer
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Summary and Status of FEE Components
Need Component Status
432 Front-End Box Tested.
1728 HV Board Prototype series in production
3465 ASDBLR Board Testing new version in preparation
1728 OTIS Board Testing new version in preparation
432 GOL/Aux Board Tested new version in preparation

6912 ASDBLR Chip Produced, awaiting delivery
1728 OTIS Chip Submitting OTIS 1.2 (final version)
Currently preparing ¼ station system test
foreseen for Oct 2004 Equip 9 modules with
electronics 2300 channels (18 FE boxes)
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Outer Tracker Electronics Time Schedule
2005
2006
2004
05/04 Submission of OTIS 1.2
06/04 Order pre-series of full electronics for
system test
09/04 Delivery of OTIS 1.2
10/04 Pre-series finished, start system test
12/05 Submission of OTIS engineering run
03/05 Start mass production of front-end boards
06/05 OTIS chips from engineering run
01/06 Start electr. assembly