Reconfigurable and Multicore Computing

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Reconfigurable and Multicore Computing

• Gregory W. Donohoe Guillermo Conde
• Electrical Computer Engineering Computer
  Science

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Moores Law
The number of transistors we can fit on a chip
will double every two years. -- Dr. Gordon
Moore, Intel Co-founder, 1965

• Implies
• Processor speed will double
• Smaller distances, signals dont have to travel
  as far
• Amount of memory will double
• Computing products shrink in size
• Prices of computing products will fall
  dramatically

Computing products will became faster, more
capable, smaller, lighter, cheaper.
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Moores Law
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Moores Law
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Eniac Computer, 1946
8 Kbits of data memory 5 KHz cycle time
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Apple iPod Touch , 2009
32 Gbytes (256 Gbits) of data memory 2 GHz cycle
time

• 32 million times more memory than Eniac
• 400,000 times faster than Enaic

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Transistors to Computers

• Transistor an tiny electronic valve or switch
• Uses electric fields to switch currents and
  voltages
• Transistors make up logic gates
• Operate on 0 and 1
• AND, OR, NOT, XOR, ...
• Logic gates make up computing modules
• Adders, subtractors, multipliers
• Memory elements arrays
• Computing modules make up system components
• Arithmetic-Logic Unit (ALU)
• Data and program memory
• Sequence control
• System components make up computers

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Sequential Computer Architecture
Executes one instruction at a time Von Neumann
bottleneck To make it go faster, reduce
instruction time.
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Computer Chips
Light Source
Projection Optics
Saw out polish wafer
Mask
Photo Lithography
Grow Si crystal cylinder

• Lithography
• Place layer of photo resist on wafer.
• Expose photo resist through mask.
• Develop photo resist.
• Process (implant, etch, etc.) is exposed areas
• Remove photo resist.

Diffusion Ion Implant Deposition Etching Growth
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Intel Pentium Processing Unit
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Chips to Systems

• Die monolithic silicon substrate
• Chip carrier substrate to which die is glued,
  I/O pads wirebonded to package pins
• Printed Circuit Board chip packages surface
  mounted or through-hole mounted, interconnected
  with etched copper lands
• System backplane or system-area-network

Die
Chip carrier
Hierarchy is planar, Similar to chip
fabrication process.
Printed circuit board
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The Shrinking Transistor The End of Moores Law?
1980s L 100 microns (micrometers) 2000s L
100 nm (namometers)

• Reaching limits of lithography features
  smaller than wavelength of light
• Gate oxide only 4 atoms thick
• Getting too expensive to shrink further

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Increase Performance through Architecture

• Von Neumann bottleneck
• Computers execute one instruction at a time
• We can no longer make them faster just by making
  the transistors smaller
• Need to find ways to execute different parts of
  the program concurrently

Multicore Network of multiple computers on a
chip Reconfigurable Computing Hardware that can
be modified on the fly to optimize it for the
particular computing problem at hand
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Multicore Processing
Replicate the processor core
Break up a computer program to do different tasks
concurrently on separate cores
Huge programming challenge!
IBM Cell Processor used in the Sony PlayStation
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Cell Processor Chip
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Reconfigurable Computing

• Design computers to be reconfigured while they
  operate
• Software commands to rewire the architecture to
  optimize it for the problem at hand

Example Compute a running average of last four
numbers in a sequence

Brute Force in Sequential Processor Add 2 5
3 7 17 (4 steps) Divide by 4 (5 steps
total) Add 5 3 7 4 19 (4 steps) Divide
by 4 (5 steps total) Add 3 7 4 6 20 (4
steps) Divide by 4 (5 steps total)
5 steps between output samples
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Pipelined Implementation
One-step delay
1/4
1/4
1/4
1/4
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Hardware Pipeline

• A new output sample at each step.
• Throughput improved 5X.

• The same kinds of structure can be used for many
  applications
• Streaming multimedia applications
• MP3, JPEG coding and decoding
• Communications channel coding
• Feedback control

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Field Programmable Processor Array
Reconfigurable processor chip for space 16
processing elements program control
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FPPA Prototype Chip
7x7 mm die 240 K logic gates About 1 millions
transistors 1/2W power dissipation
Goal high throughput at with low power Getting 3
GOPS/watt on NASA-specified computations
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FPPA Project
Funded by NASA for space applications
Joint effort Electrical and Computer
Engineering and Computer Science

• Project elements
• Architecture and Chip Design
• System Software
• Applications

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FPPA Project

• Architecture Chip Design
• Designed in VHDL Hardware Description Language
• Behavior verified against simulator
• Synthesized to gates and transistors using
  Computer Aided Design software

• System Software
• Simulator written in C
• Design entry tools
• FPPAFlo graphical design tool
• Single Assignment C (SA-C, or Sassy) compiler
• Low-level language translators configuration and
  run-time assemblers

• Applications demonstrated in simulator or
  hardware
• Spacecraft instrument calibration
• Hyperspectral Imager data conversion
• Cloud detector
• Remote-sensing pre-processor

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FPPA Student Participants
Graduated David M. Buehler, PhD, EE, Spring,
2004. A Methodology for Designing and Analyzing
Fixed-Point Implementations of Computational Data
Paths. Tao Zhao, MSEE, 2009. Dynamic Power
Management for a Reconfigurable
Processor. William Walker, MS Comp E, Spring
2008. The Field Programmable Processor Array a
Study of the Design and Test Process. Christopher
Canine, MSEE, Fall 2007. A Low Power,
Radiation-Tolerant Reconfigurable Computing
Platform for Space. Yichao Ye, MEngr, University
of Idaho, Summer, 2006. Implementing Elementary
Functions on a Reconfigurable Processor. Victor
H. Cordero Calle, MSEE, 2006. Data Path
Computations for the Solar Viewing Interferometer
Prototype. Enrique Coen-Alfaro, MSEE, Spring,
2004. Crossbar Architectures for VLSI Systems A
Comparative Study. Jagdish Sabde, MSEE, Spring,
2004. Sensor Data Processing on a Reconfigurable
Processor. Frank Jones, BSCS, 2007 Now MS
student in CS Paul Mawhirter, BSCS, 3008 Now MS
student in CS Current Guillermo Conde, PhD
student, ECE Damian Sanchez, MS student, ECE John
Geidl, MS student, ECE
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Conclusion

• Computers have grown faster, smaller, more
  powerful over the last 6 decades, and penetrated
  all aspects of our lives
• Largely due to Moores Law making transistors
  smaller faster

Moores Law seems to be reaching physical
economic limits

• One way to keep progress moving new
  architectures that exploit parallelism
• Multicore multiple computers on a chip
• Reconfigurable computing optimize architecture
  on the fly
• Hybrid computing combine these and other
  approaches

Great challenges and opportunities await computer
scientists and engineers who can figure out how
to program these new kinds of computers to take
advantage of their potential.