RF Packaging Requirements

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RF Packaging Requirements
José Schutt-Ainé Associate Professor University
of Illinois, Urbana
ECE 482
21, March 2000
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OUTLINE
Challenges of Electronics Industry
Requirements for RF/Mixed Signal Design
Requirements for High-Speed Digital Design SOC
versus SOP Signal Integrity Issues Design,
Modeling Simulation National Course for
Signal Integrity
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Future System Needs and Functions
Auto
Digital Wireless
MEMS
Analog, RF
Computer
Consumer
High-speed Digital
High bandwidth
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Microelectronics, Systems Packaging Environment
Semiconductor Unprecedented
Innovations in CMOS, Si-Ge,Copper Wiring
Fundamental technical Limits
Electronic Systems Computers, telecom
Consumer Products Merge Portable,
Wireless, Internet Accessible Very
Low Cost Very High Performance
Microelectronic Packaging High Cost,
Low Performance, Low Reliability Lack
of Skilled Human Resources
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The Interconnect Bottleneck
Al 3.0 mW -cm Cu 1.7 mW -cm SiO2
k 4.0 Low k k 2.0 Al Cu .8m
Thick Al Cu Line 43m Long
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Semiconductor Technology Trends
Observations Roadmap
timeline acceleration Innovative methods will
be needed
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The Interconnect Bottleneck
Technology Generation
Response Time
MOSFET Intrinsic Switching Delay
1.0 um
10 ps
1 ps
0.01 um
100 ps
1 ps
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Chip-Level Interconnect Delay
Logic threshold
Logic threshold
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Electronic Design Automation
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Design Requirements
New Methodologies Wireplanning Efficient
Extraction Tools Efficient Simulation Tools
High-Performance Platforms Availability of
Libraries
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Interconnect Schemes
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Wire Bonds
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Pin Grid Array
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Package Inductance Capacitance
Component Capacitance Inductance
(pF) (nH) 68 pin plastic DIP pin 4
35 68 pin ceramic DIP pin 7 20 68 pin
SMT chip carrier 2 7 No ground
plane capacitance is dominated by wire to wire
component. With ground plane capacitance and
inductance are determined by the distance between
the lead frame and the ground plane, and the lead
length.
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Package Inductance Capacitance
Component Capacitance Inductance
(pF) (nH) 68 pin PGA pin 4
35 256 pin PGA pin 7 20 Wire
bond 1 1 Solder bump 0.5
0.1 No ground plane capacitance is
dominated by wire to wire component. With
ground plane capacitance and inductance are
determined by the distance between the lead frame
and the ground plane, and the lead length.
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Flip Chip Pin Grid Array(FC-PGA)
Bumped Die
Package
Body
Pins
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Packaging for Signal Integrity
Dominated by transmission lines and reactive
elements Consist of matching, terminating lines
and optimizing interconnect geometries Digital
Minimize delay RF Increase bandwidth
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Microstrip
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WAVE PROPAGATION
l
Wavelength
propagation
velocity
l


frequency
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Why Transmission Lines ?
Transmission line behavior is prevalent when the
structural dimensions of the circuits are
comparable to the wavelength.
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Why Transmission Lines ?
High
Frequency
Circuit Board
Low
Frequency
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Types of Transmission Lines
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Telegraphers Equations
L Inductance per unit length. C Capacitance
per unit length.
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(No Transcript)
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Metallic Conductors
Metal
s (W-1 m-1 10-7) Silver
6.1 Copper 5.8 Gold
3.5 Aluminum 1.8 Tungsten
1.8 Brass 1.5 Solder 0.7
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Damascene Process (IBM)
Key Features
- 6 layers of metallization - Copper - Channel
length of 0.12 um - Resistivity 45 lower than
Al - Prevent copper from diffusing into Si
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Crosstalk Noise
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Crosstalk Noise in Digital Circuits
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RF Frequency Bands
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Requirements and Challenges for Analog RF
Systems
Dominated with Passive Reactive Components
Scale with Frequency rather than Technology
Packaging Dominated by Transmission Lines A/D
Packaging Requirements Very Stressing High
Quality Factor for Resonant Systems Reduce or
control Mixed-Signal Noise
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Skin Effect in Microstrip
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Loss in RF Circuits
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Skin Effect
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Consequences of Skin Effect
Increased Latency Increased Attenuation
Increased Dispersion Increased Distortion
REDUCED BANDWIDTH
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Crosstalk Noise in RF Circuits
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Mixed Signal Noise
? Simultaneous switching and inductance
(Leff) ? Leff is f( current magnitude and
direction) ? Interactions between noise generated
by power/ground and signal paths
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Transceiver System
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Basic Components of a Wireless Handset
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Advantages of SOC
Fewer Levels of Interconnections Reduced Size
and Weight Merging of Voice, Video, Data,...
Arguments against SOC
Challenges too Big Legal issues
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Challenges for SOC
Different Types of Devices Single CMOS
Process for RF and Digital Design Methodology
not available EDA Tools cannot handle level of
complexity Intellectual Property Signal
Integrity High-Power Requirements of PA
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Proposed Solutions for Analog RF Systems
MEMS (filters, capacitors, switches) High-Tc
Superconductors Flip-Chip Packaging SOC ? SOP
?
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Integration of MEMS with MMICs
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Voltage-Controlled Oscillator
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MEMS Tunable Capacitor
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Limitations of RF-MEMS
Relatively low Q Switching too slow (MEMS
switches) Brownian motion (tunable
capacitors) High actuation voltage (switches)
Low capacitance
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Proposed Solutions for Analog RF Systems
MEMS (filters, capacitors, switches) High-Tc
Superconductors Flip-Chip Packaging SOC ? SOP
?
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System on a Chip (SOC)
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SLIM Approach to SOP (GaTech)
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SOP vs SOC
SOC
SOP
Low cost consumer products (lt200)
YES
YES
Portable products (200-2000)
YES
NO
Single processor products (1-5K)
YES
NO
High Performance Products (gt5K)
NO
YES
Automotive and Space Applications
NO
YES