What gives semiconductor executives sleepless nights

1

• What gives semiconductor executives sleepless
  nights?

YIELD
2

• What causes yield problems?

Defects
3

• How does design get involved?

Variability
4
Defect/Design Learning fromElectrical Test

• Dr. Bernd Koenemann
• Mentor Graphics Corporation

5
Agenda

• Introduction
• Defects and Technology Challenges
• Defect Learning
• Background
• Enhanced Learning with Test
• Total Analysis Vision
• Summary

6
Introduction CMOS Technology
Source Ian Young, Intel, MARCO/DARPA FCRP
Workshop, 2003
7
Introduction The Yield Ramp Challenge
Source R. Madge, ITC 2004
8
Defect Types and Potential Sources
Static
Environmental (Vdd, T, PLL, SEU)Coupling Noise,
Signal IntegrityHotE, Electromigration, Negative
Bias Threshold Instability (NBTI)
? Particle and otherSingle Event Upsets (SEU)
Dynamic
From R.Puri, IBM
9
Spot Defects Particles

• Caused by dirt/impurities, and/or
  equipment/material problems
• E.g., particle contamination causes a short
• May be visible to in-line inspection tools
• Can be characterized by test structures
• Create catastrophic or parametric defects
• Area-sensitive (critical area)

From Skumanich and Ryabova, ASMC 2002
10
Critical Area Concept

• Area into which the center of a defect must fall
  to create
• Shorts for additive material
• Opens for subtractive material

CA for additive material
CA for subtractive material
11
Critical Area Example
From Christie, P. de Gyvez
12
Critical Area and Yield

• Particle-size distribution and defect types must
  be taken into account
• Monte-Carlo simulation
• Analytical methods

Layout Defect Sensitivity
Probability of Failure
0.35
1.2
0.3
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0.25
0.8
0.2
Sensitivity
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Defect size (10um)
Defect size
Defect size
From Christie, P. de Gyvez
13
Feature-Based Yield
Particle Defect-driven vs. Feature-driven
Yield Failure to form features replaces particle
defects as the problem
100
Traditional defect-limitedyield
90
Product yield
80
70
60
0.8?m
0.5?m
0.35?m
0.25?m
.18?m
.13?m
90nm
From PDF Solutions
14
Sub-Wavelength Lithography
Lithography
Lithography
365nm
365nm
Wavelength
Wavelength
248nm
248nm
193nm
193nm
180nm
180nm
130nm
130nm
90nm
90nm
65nm
65nm
FeatureSize
45nm
45nm
32nm
32nm
13nm
13nm
EUV
EUV
1980
1990
2000
2010
2020
Source Borkar et al., GVLSI 2002 Grobman, DAC
2001
15
Optical Proximity Effects

• Optical Proximity Correction (OPC) mitigates
  problem but is very complex

Original Layout 0.18 mm
Silicon Image
Image from Pati, DAC99
16
Layout vs. Post-OPC Silicon Shapes

• Affects performance, checking, parasitics/extracti
  on

From Rencher and Schellenberg, EE Design, 2003
17
OPE/OPC Example
Image from B. Cory
18
Impact of OPE/OPC

• Affects transistor performance, matching, and
  extraction
• Is the major deterministic source of device
  variability, e.g.,
• Gate length variation
• Line end pullback
• Widening/Thinning, etc.
• Complicates performance estimation/bin sort yield

Source Pack et al., SPIE 2003
19
More Sources of Variability
From Borkar et al., GVLSI 2002 Grobman, DAC 2001
20
Metallization Issues
Large topographical variation caused by soft pad
and mechanical properties
IsolatedTransistor
Dense Array
CMP,SOG
Contact Overetch causes leakage
RIE
Etc.
Source R. Pack, Cadence
21
Systematic Physical Defects
From Weber, at al., MICRO
22
Etc.

• Overall static variability is on the rise

From S. Nassif, ISPD 2004
23
Impact of Static Variability
Frequency 30 Leakage Power 5-10X
From Borkar et al., GVLSI 2002
24
Dynamic Variability

• Voltage
• Activity change
• Power deliveryRLC
• Dynamicns to 10-100 uSec
• Within die
• Temperature
• Change in activity and ambient
• Dynamic 100s of uSec to mSec
• Within die

25
Temperature Profile Example

• Varies spatially and with time (switching
  activity)

From C. Visweswariah, IBM
26
Impact of Temperature Variability
From S.A. Bota, et al., ITC2004
27
Impact of IR Drop and Power Supply Noise

• Normalized circuit delay (simulated)

w/ supply noise
w/ IR drop
w/o supply noise
From Y.M. Jiang and K.T. Cheng, UCSB
28
Design Process Changes Due to Variability
System
Logic
Circuit
Deterministic
Layout
Models
Manu-facturing
Characterization
From R.Puri, IBM
29
Variability and Design
Chip behavior in the face of environmental and
manufacturing variations
Critical area Voronoi diagrams Redundant via
insertion Wire bending/spacing
Statistical timing Yield prediction Design
centering Design for manufacturability
From C. Visweswariah, IBM
30
Statistical Timing Analysis
From C. Visweswariah, IBM
31
First Summary

• Yield is becoming a key element of new design
  flows

Design Planning Flow
Post GDSII Flow
Pre-Layout Flow
Physical Design Flow
Customer Netlistw/o IO and Test
Initial STA
Detailed Route
Final Masks

DRC/LVS
Mask Prep

Logic Synthesis

Timing Closure Loop

Global Route

Dummy Fill

OPC
Test Insertion
Floor Planning

Final STA
GDSII Generation
Source, R. Madge, ITC 2004
32
Design versus Reality
Manufacturing
Design
Reality Check?
Reality Check?
33
Defect Learning

• Background
• Inspection/metrology
• Test/characterization Vehicles
• Yield management systems
• Enhanced learning with test
• Debug/diagnostics/failure-analysis
• Statistical processing

34
Inspection/Metrology

• Scanning for visible defects (mask/wafer)
• Special equipment
• Creates defect maps
• Measurement/tracking of process parameters
• Metrology equipment for specific process issues
  (e.g., surface planarity, oxide thickness, etc.)
• Equipment logs
• Measurement of circuit parameters
• Scribe-line (KERF) monitors
• Dedicated monitor structures
• On-chip monitors (e.g., PSRO, etc.)

35
In-Line Inspection (Surface Scan)
Equipment
Results File
e.g., Defect x-y-coordinates Defect size Defect
classification Etc.
Detailed Image
Wafer Map Image
From Multiple Sources
36
In-Line Inspection Characteristics

• Visualizes defects
• Defect densities
• Spatial distributions
• Time-consuming
• Limited subset of wafers/layers/process steps
• No immediate indication of yield impact if defect
  density is within expectations
• Limited scope
• Not all defects are visible
• Significance of non-visible defects is growing
  (ITRS)

37
Test Vehicles

• Simple monitor structures for specific defect
  types
• E.g., metallization, vias, contacts, etc.
• Sophisticated design/process characterization
  monitors
• E.g., multiple defect types, representative of
  design/library elements, etc.

38
Simple Serpentine Test Structure

• Suitable for measuring metallization defect
  densities

From Hess, et al., 2001
39
Sophisticated Test Vehicles

• Combination of multiple monitor structures
• Targeting random and feature-based defects
• Integrated into comprehensive characterization
  flow

From PDF Solutions
40
Test Vehicle Characteristics

• Extract defect densities and yield sensitivities
• Multiple defect categories
• Representative circuit structures can reveal
  impact of defects on electrical fails
• Costly
• Dedicated designs that must be processed through
  line
• Design time, limited runs, etc.
• Limited scope
• Only detect/measure defect rates related to the
  circuit structures provided in the test vehicle
• May not include all yield-sensitive features
  found in real product designs

41
Yield Management Systems

• Infrastructure for monitoring and analyzing yield
  issues
• Data collection
• Data warehousing
• Data mining/analysis
• Increasingly comprehensive
• Many data types (e.g., logistics, equipment,
  metrology, binning, etc.)
• Many analysis routines (e.g., queries, report
  generation, visualization, alert automation,
  etc.)
• Customizable (e.g., database extensions,
  scripting/APIs, etc.)

42
Example E-Diagnostics Infrastructure
From Kot and Yedatore, Semi International, 2003
43
Example Data Visualization (from Test)
Source, R. Madge, ITC 2004
44
Yield Management Systems Characteristics

• Very comprehensive
• Logistics, equipment, events, metrology, binning,
  etc.
• Can enable fast problem detection/correction
• Available and flexible
• Offered by multiple vendors
• Extendible data bases, queries, analyses,
  visualizations
• Limited scope
• May not have access to intra-chip design data
• Analysis resolution primarily at wafer-map level
• Extending resolution to intra-chip design/process
  interactions generally requires home-grown
  add-ons (happening in several places)

45
Why Better Resolution from Product Test?

• Yield limiters may buried inside the product
  design
• Very context-sensitive and design specific
• Non-visual and not represented in test vehicles

WorstCaseSpec
StatisticalSpec
EDAModel
Probability
Parameter
46
The New Role of Test

• Test may be the first real opportunity to uncover
  the statistical impact of new catastrophic and
  parametric defect sources
• Test can become a key tool for statistical design
  verification and design/yield learning

47
Diagnostics

• Finding the root-cause of a particular test fail
• Characterizing the failing behavior
• Localizing the most likely problem area
• Integral part of
• Silicon debug
• Failure analysis

48
Flow/Equipment/Tools for Silicon Debug
From S. Maher
49
Example Equipment of the Trade
Source Credence/NPTest
50
Time-Resolved Backside Imaging
.13mm Inverter Chain Image . 2mm Image
Resolution (Through Si Backside)
Source Credence/NPTest
51
Memories

• Memories are relatively easy to diagnose
• Regular logic structures (word, bit)
• Regular physical structures (row, column)
• Bitmapping (i.e., logging the failing logic
  words/bits) is supported by Automatic Test
  Equipment (ATE) and Built-In Self-Test (BIST)
• Stand-alone and embedded memories in product
  chips have been and are important defect learning
  vehicles

52
Memory Diagnostics

• Log complete fail bitmaps from ATE/BIST
• Convert logical maps to physical maps
• Requires access to physical layout, bit/address
  scrambling tables, etc.
• Visualize/analyze logical and physical fail bit
  maps
• Look for characteristic patterns (e.g.,
  single-bit fail, row/column fail, etc.)
• Overlay with other data, e.g.,
• Layout (GDS II)
• Defect maps from in-line inspection
• Requires reticle/wafer map to translate to/from
  wafer-level coordinate system
• Initiate Failure Analysis (FA)

53
Memory Fail Bitmap Example
54
Overlay of Bitmap and Defect Map
55
Logic

• Logic is more difficult to diagnose
• Non-regular
• Limited visibility of internal circuit states (no
  equivalent to direct bitmapping as for memories)
• Traditionally has been a time-consuming manual
  effort
• Significant automation possible for designs with
  scan
• Enhanced state visibility at scan cells and
  primary outputs
• However, still no direct mapping of logic outside
  scan cells
• Failing scan cells may not be actual problem
  locations

56
Example
From A. Weber, Semi International, 2004
57
Logic Diagnostics (with Scan)

• Log some number of fail sets (failing scan cells
  and primary outputs) from ATE or BIST
• Run logic fault isolation software
• Create gate-level callouts (net/pin names, fail
  type) most likely near the problem area
• Visualize callouts in layout
• Requires link between gate-level netlist and
  layout (e.g., from running LVS)
• Overlay callouts with defect maps or other
  information
• Requires translation to/from wafer-level
  coordinates
• Initiate Failure Analysis (FA)

58
Diagnostic Flow for FA
DesignDB
Netlist
Fail Maps
Run Test withFail DataCollection
Logic Fault Isolation
Determine Failing Net Location
Visualize Failing Net
IdentifyDie ofInterest
NavigateFIB/SEM toLocation
Determine Cause of Failure
From D. Abercrombie
59
Fault Isolation Software
Netlist,Fault Models
Fault Simulation
Simulatedfail sets
TestPatterns
Compareandrank
Callouts
ATE/BIST
Fail sets
Note Fault simulation can be run ahead of time
to pre-calculate a fault dictionaryor after the
fact during diagnostics
60
Callout Example
Note from IBM TestBench
61
Link to Layout
Note from Mentor Graphics
62
Overlay with Defects (Logic Bitmapping)
Fail Net Visualization
Note from LSI Logic
63
Statistical Diagnostics for Logic

• Emerging defect/yield learning method for complex
  logic designs
• Implement comprehensive fail set logging for
  initial ramp and for volume production test
• Run logic fault isolation on all fail sets (could
  be thousands per day)
• Write all callout information into database
• Statistically sort, analyze, and visualize the
  cumulative callout information, e.g.,
• Query by cell-type, cell-instance/location, etc.
• Stack results on chip layout, reticle, and/or
  wafer map
• Compare with yield predictions
• Etc.

64
Example Stacked Callout Visualization
Note from LSI Logic
65
Example Sorting by Cell Type
FromD. Apello, et al., ST Micro
66
Example Sorting by Cell Instance/Location
FromD. Apello, et al., ST Micro
67
Indicted Area
FromD. Apello, et al., ST Micro
68
Underlying Problem
FromD. Apello, et al., ST Micro
69
State of the Art

• Statistical diagnostics of logic fails are a
  rapidly emerging design/defect learning
  technology
• Learning design-specific issues from product
  chips
• Statistical relevance with large number of
  samples
• Complement/enhance existing fab-oriented yield
  management systems
• Add intra-chip resolution and visibility
• Complement/enhance DFM and yield modeling
• Provide feedback and calibration
• Most existing solutions are home-grown at IDMs
• Challenging data security/access issue for
  fabless/foundry
• No integrated commercial solution yet

70
Statistical Analysis Context
From Philips
71
Conclusion Vision of an Integrated Solution
Debug/FA Lab
Yield Management
Applications
Applications
APIs/Utilities
APIs/Utilities
Design Database
Data Warehouse
WIP, Metrology, Test,
Design, design analysis,
Inspection, etc.
design intent, etc.
72
The End