Introduction to CMOS VLSI Design Lecture 3: DC

1
Introduction toCMOS VLSIDesignLecture 3 DC
Transient Response
David M. Zar Washington University in St.
Louis Based on original work, with permission,
by David Harris Harvey Mudd College
2
Outline

• Pass Transistors
• DC Response
• Logic Levels and Noise Margins
• Transient Response
• RC Delay Models
• Delay Estimation

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Activity

• 1)     If the width of a transistor increases,
  the current will 
• increase decrease not change 
• 2)     If the length of a transistor increases,
  the current will
• increase decrease not change
• 3)     If the supply voltage of a chip increases,
  the maximum transistor current will
• increase decrease not change
• 4)     If the width of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 5)     If the length of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 6)     If the supply voltage of a chip increases,
  the gate capacitance of each transistor will
• increase decrease not change

increase
decrease
increase
increase
increase
not change
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Pass Transistors

• We have assumed source is grounded
• What if source gt 0?
• e.g. pass transistor passing VDD

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Pass Transistors

• We have assumed source is grounded
• What if source gt 0?
• e.g. pass transistor passing VDD
• Vg VDD
• If Vs gt VDD-Vt, Vgs lt Vt
• Hence transistor would turn itself off
• nMOS pass transistors pull no higher than VDD-Vtn
• Called a degraded 1
• Approach degraded value slowly (low Ids)
• pMOS pass transistors pull no lower than Vtp
• Transmission gates are needed to pass both 0 and
  1

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Pass Transistor Ckts
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Pass Transistor Ckts
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DC Response

• DC Response Vout vs. Vin for a gate
• Ex Inverter
• When Vin 0 -gt Vout VDD
• When Vin VDD -gt Vout 0
• In between, Vout depends on
• transistor size and current
• By KCL, must settle such that
• Idsn Idsp
• We could solve equations
• But graphical solution gives more insight

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Transistor Operation

• Current depends on region of transistor behavior
• For what Vin and Vout are nMOS and pMOS in
• Cutoff?
• Linear?
• Saturation?

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nMOS Operation
Vtn
Vtn Vgsn Vtn
Vtn Vgsn Vtn
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nMOS Operation
Vgsn Vin Vdsn Vout
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nMOS Operation
Vgsn Vin Vdsn Vout
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pMOS Operation
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pMOS Operation
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pMOS Operation
Vgsp Vin - VDD Vdsp Vout - VDD
Vtp lt 0
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pMOS Operation
Vgsp Vin - VDD Vdsp Vout - VDD
Vtp lt 0
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I-V Characteristics

• Make pMOS wider than nMOS such that bn bp

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Current vs. Vout, Vin
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Load Line Analysis

• For a given Vin
• Plot Idsn, Idsp vs. Vout
• Vout must be where currents are equal in

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Load Line Analysis

• Vin 0

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Load Line Analysis

• Vin 0.2VDD

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Load Line Analysis

• Vin 0.4VDD

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Load Line Analysis

• Vin 0.6VDD

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Load Line Analysis

• Vin 0.8VDD

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Load Line Analysis

• Vin VDD

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Load Line Summary
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DC Transfer Curve

• Transcribe points onto Vin vs. Vout plot

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Operating Regions

• Revisit transistor operating regions

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Operating Regions

• Revisit transistor operating regions

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Beta Ratio

• If bp / bn ? 1, switching point will move from
  VDD/2
• Called skewed gate
• Other gates collapse into equivalent inverter

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Noise Margins

• How much noise can a gate input see before it
  does not recognize the input?

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Logic Levels

• To maximize noise margins, select logic levels at

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Logic Levels

• To maximize noise margins, select logic levels at
  
• unity gain point of DC transfer characteristic

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Transient Response

• DC analysis tells us Vout if Vin is constant
• Transient analysis tells us Vout(t) if Vin(t)
  changes
• Requires solving differential equations
• Input is usually considered to be a step or ramp
• From 0 to VDD or vice versa

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Delay Definitions

• tpdr
• tpdf
• tpd
• tr
• tf fall time

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Delay Definitions

• tpdr rising propagation delay
• From input to rising output crossing VDD/2
• tpdf falling propagation delay
• From input to falling output crossing VDD/2
• tpd average propagation delay
• tpd (tpdr tpdf)/2
• tr rise time
• From output crossing 0.2 VDD to 0.8 VDD
• tf fall time
• From output crossing 0.8 VDD to 0.2 VDD

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Delay Definitions

• tcdr rising contamination delay
• Minimum delay from input to rising output
  crossing VDD/2
• tcdf falling contamination delay
• Minimum delay from input to falling output
  crossing VDD/2
• tcd average contamination delay
• tcd (tcdr tcdf)/2

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Simulated Inverter Delay

• Solving differential equations by hand is too
  hard
• SPICE simulator solves the equations numerically
• Uses more accurate I-V models too!
• But simulations take time to write, may hide
  insight

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Delay Estimation

• We would like to be able to easily estimate delay
• Not as accurate as simulation
• But easier to ask What if?
• The step response usually looks like a 1st order
  RC response with a decaying exponential.
• Use RC delay models to estimate delay
• C total capacitance on output node
• Use effective resistance R
• So that tpd RC
• Characterize transistors by finding their
  effective R
• Depends on average current as gate switches

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Effective Resistance

• Shockley models have limited value
• Not accurate enough for modern transistors
• Too complicated for much hand analysis
• Simplification treat transistor as resistor
• Replace Ids(Vds, Vgs) with effective resistance R
• Ids Vds/R
• R averaged across switching of digital gate
• Too inaccurate to predict current at any given
  time
• But good enough to predict RC delay