IBIS FUTURES COMMITTEE MULTILINGUAL MODEL: DIGITAL PORT ISSUES

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IBIS FUTURES COMMITTEEMULTILINGUAL
MODELDIGITAL PORT ISSUES

• Ian Dodd
• 25th March 2004

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Digital Multilingual Ports

• Standard Digital Ports
• Inputs
• D_enable
• D_drive
• Outputs
• D_receive

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Digital Port Type Concerns

• VHDL-AMS and Verilog-AMS port types must match
  exactly between the SI tools top level circuit
  and user multilingual model.
• It is assumed we will ensure this by requiring
  model providers to use standard port types
• It is assumed the reference to IEEE
  Std_logic_1164 enforces one (9 state) digital
  port type for VHDL-AMS
• We need to specify something equivalent for
  Verilog-AMS digital ports
• Do we need to also specify port type/nature for
  analog ports.

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Allowed Digital Logic Levels

• Propose we limit the logic states that are legal
  for the standard digital ports
• Inputs
• VHDL-AMS 1, 0 or Verilog-AMS equivalent
• Outputs
• VHDL-AMS 1, X, 0 or Verilog-AMS equivalent

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