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Architectural Investigation of XCTL by URCA

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Architectural Investigation. of XCTL by URCA. Milo Cvetanovic, Dragan Bojic ... identify groupings of objects that posses common attributes Burmeister (1998) ... – PowerPoint PPT presentation

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Title: Architectural Investigation of XCTL by URCA


1
Architectural Investigationof XCTL by URCA
  • Miloš Cvetanovic, Dragan BojicFaculty of
    Electrical Engineering
  • University of Belgrade
  • cmilos, bojic_at_etf.bg.ac.yu

2
Agenda
  • Introduction to URCA
  • Formal Concept Analysis
  • XCTL project
  • Reverse engineering process
  • Results comparison Conclusion

3
Introduction
  • Use case Design Recoveryby means of Formal
    Concept Analysis (URCA)
  • Recovers all mandatory elementsof the Rational
    Unified Process model template
  • Static analysis ? basic model elementsDynamic
    analysis ? behavioral aspectsConcept analysis ?
    relationships and roles

Static Analysis
UMLModel
TestCases
DynamicAnalysis
ConceptAnalysis
4
Formal Concept Analysis
Concept Analysis is used to identify groupings of
objects that posses common attributes
Burmeister (1998).
A1 A2 A3 A4 A5 A6 A7 A8
O1 X X            
O2     X X X      
O3     X X   X X X
O4     X X X X X X
Context relation
Partial orderviasuper subconcept ordering
Concept lattice
5
Interpretation
  • Object maps to Function in code (O ? F)(both
    class member and global)
  • Attribute maps to Use case (A ? U)
  • Context relation implements
  • There exist at least one test case
  • that executes F and exercise U
  • Concept contains
  • - Set of use cases cardinality 1 in ideal
    case
  • - Set of related functions

6
XCTL Project
  • An application for controllinglaboratory
    equipment at Max Planck Institute
  • A reference software reengineering projectat the
    Humboldt University
  • XCTL classical Windows application
  • - 46 classes
  • - 496 member functions and global functions
  • - 38,5 KLOC

7
Reverse Engineering Process (1)
  • STEP 1Identify architecturally relevant use
    cases
  • STEP 2
  • Define test cases that exercise each use case
  • - Start Exit - Diffraction/Reflection Area
    Scan
  • - Motor control - Diffraction/Reflection Line
    scan
  • - Detector use - Representation of measured
    data
  • - Flow control - Automatic adjustment
  • - Topography - Manual adjustment
  • - General Attitude - Half-width measure

8
Reverse Engineering Process (2)
  • STEP 3
  • Collecting dynamic informationby executing
    application for each use case
  • - Profiling data (function execution count)
  • - Function Activation Tree ( UML interaction
    diagrams)
  • We define some operation on dynamic data
  • - Differing execution count (for extends
    relations differentiation)
  • - Function filtering (needed to decompose
    interactions)
  • - Elimination of repeating calling sequences
    (loops elimination)

9
Reverse Engineering Process (3)
  • Example of operations over activation tree

10
Reverse Engineering Process (4)
  • STEP 4
  • Construction of Context relation
  • STEP 5
  • Construction of Concept latticeby means of
    Formal Concept Analysis

11
Reverse Engineering Process (5)
  • Interpretation of the Concept lattice

Root
Diffraction/ReflectionScan
Generalized(abstract) use cases
Area Scan
Line Scan
Motor Control
Concreteuse cases
Device Control
Included use cases (shared functionality)
Leaf
12
Reverse Engineering Process (6)
  • STEP 6
  • Construction of the initial UML model
  • based upon the results of the Static analysis
  • STEP 7
  • Supplementing of the initial UML model
  • based upon the results of Concept analysis

13
Results comparison
14
Result comparison
15
Result comparison Conclusion
  • Similarities
  • Same grouping criterion (use case realizations)
  • Differences
  • Class roles are not present in the manual
    analysis
  • Human intelligent abstraction logic
  • Hierarchies as a level of abstraction

16
Architectural Investigationof XCTL by URCA
  • Miloš Cvetanovic, Dragan BojicFaculty of
    Electrical Engineering
  • University of Belgrade
  • cmilos, bojic_at_etf.bg.ac.yu
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