Semiconductor Manufacturing Technology

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EE-354
Integrated Circuit Technology
Characteristics of Semiconductor Materials and
Basic Device Physics(Part 2)

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Note This lecture repeats some of the first
lecture, but uses different figures and a
slightly different approach to show the various
types of device physics.
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Basic Symbol and Structure of the pn Junction
Diode
Figure 3.5
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Open-Circuit Condition of a pn Junction Diode
Doping creates Electric Field and Intrinsic
Potential
Figure 3.6
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Reverse-Biased PN Junction Diode
Figure 3.7
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Forward-Biased PN Junction Diode
Figure 3.8
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Forward and Reverse Electrical Characteristics of
a Silicon Diode
Intrinsic Potential (depends on doping
concentration)
Figure 3.9
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MOS Device Physics

• Gate is TOTALLY insulated from Semiconductor
• Three components are Source (S), Gate (G) and
  Drain(D)
• Current will be Minority Carriers of substrate
  under Gate!
• Quiescent State Gate is reverse voltage of
  substrate (- for p-type and for n-type.) This
  repels/depletes silicon below gate (between S and
  D) of any minority carriers.
• Conducting State Gate is same as substrate (
  for p-type and for n-type substrate).
• Gate pulls minority carriers from substrate to
  thin layer (5nm) connecting Source and Drain with
  their majority carriers.
• Forward bias of Source/Gate injects majority
  carriers into thin layer.
• Bias of Gate/Drain creates field that pulls
  majority carriers into Drain.

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Two Types of MOSFETs
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Biasing Circuit for an NMOS Transistor
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NMOS Transistor in Conduction Mode
Figure 3.17
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Example of Characteristics Curves of an
N-channel MOSFET
Figure 3.18
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Biasing Circuit for a P-Channel MOSFET
Figure 3.19
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PMOS Transistor in Conduction Mode
Lamp ON
Figure 3.20
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Schematic of a CMOS Inverter
NOTE No Current (no heat) Vdd to Vss under any
logic levels.
The MOST FUNDAMENTAL Circuit in IC Technology !
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Top View of CMOS Inverter
IN
OUT
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Cross-section of CMOS Inverter
Field Oxide insulates adjacent devices from
each other
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Building from Inverter to NOR Circuit
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Comparison of Enhancement and Depletion Mode
MOSFETs
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CMOS Inverter Latch-Up (Self Destruction)
Because an NPN and a PNP device are adjacent, it
is possible for the NP (forward bias) of one
device to couple to the PN (forward bias) of the
other device. This would lead to a diode
characteristic and not a MOS transistor effect.
The result is a self burn-out of the coupled
devices. The coupling between the two devices may
be controlled by keeping the substrate doping low
enough to prevent significant minority carriers
to build up (high resistance between the NP and
the PN junctions). (see next slide for
illustration)
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Latchup in CMOS Devices
Parasitic Junction Transistors within a CMOS
Structure
Figure 3.27
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Bipolar Device Physics

• Three components are Emitter (E), Base (B) and
  Collector(C)
• Gate is connected to Semiconductor (produces
  heat)
• Current will be Minority Carriers of substrate.
• Emitter doping gtgt Base doping. Base is very
  narrow. This means electric field penetrates deep
  into base region, almost to B/C junction.
• Quiescent State Emitter/Gate at same bias. No
  current. E/B current is limited by intrinsic
  field, B/C junction is reverse-biased.
• Conducting State VE lt VB ltlt VC (NPN type)
• Emitter/Base Forward Biased. Base/Collector
  Reverse Biased.
• This Bias is the same as for MOS device.
• Emitter/Base field extends almost to Collector.
  Forward bias injects minority carriers into
  narrow Base. These carriers immediately drift to
  B/C junction, and the B/C electric field
  accelerates them into Collector.

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Two Types of Bipolar Transistors
Figure 3.10
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NPN Transistor Biasing Circuit
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PNP transistor biasing circuit
Figure 3.12
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Cross Section of an NPN Bipolar Device
Figure 3.13