Versatile Calculator

1
Versatile Calculator

• By
• Dilip Patlolla
• Roopa Channappa
• Electrical and Computer Engineering
• University of Tennessee
• Knoxville

2
Abstract-Versatile Calculator

• This Project deals with the design of a block,
  which is part of the MIPS (Micro Computer without
  Interlocked Pipeline Stages) Processor
  architecture. In this project, a Data Path and
  Control Unit are implemented to carry the design.
  The block is designed to work as a calculator
  where the user provides the instruction and the
  data on which the operation is to be performed.
• It involved the design, simulation, and
  demonstration using Xilinx and Altera
  technologies using Field Programmable Gate Arrays
  (FPGA). The system was described in Very High
  speed integrated circuit Description (VHDL) and
  was synthesized using Synplicity tools. After
  this post simulation was done and the design was
  placed and routed on a SPARTAN-3 board using
  Xilinx and Altera tools.

3
Design Flow
System Requirements

Architectural Specifications
Behavioral Description
Structural Description
Pre Simulation
Synthesis
Libraries
Simulation
Placement and Routing
Physical Implementation
4
Specifications

• Instruction Memory
• Splitter
• Register
• ALU
• Display Controller
• BIST
• Clock

5
Block Diagram
BIST
Control Unit
opcode
input
go
digit
do
Instruction splitter
Register
ALU
Display Controller
data1
opcode
carry
RESET
Data 2
borrow
MUX
seg
Data 1
result
BIST
CLOCK
clock
Result to memory
6
System Requirements

Address(30) Slide switches(k13,k14,j13,J14)
4
8
FPGA
1
Clock (T9)
1
Seven Segment Display
BIST
8
1
DO(M13)
1
Go(M14)
8
1
RESET
7
Instruction Set Memory

8
Instruction set
15
0
9
4
10
Opcode
DATA 1
DATA 2

• The instruction set is of 16 bit width
• With three parts
• DATA 1 of 6 bit length
• DATA 2 of 6 bit length
• Opcode of 4 bit length

9
Opcodes

• Operations
• 0000 add data 1 data 2
• 0001 subtract data 1 data 2
• 0010 increment data1 1
• 0011 decrement data1 - 1
• 0100 complement not data1
• 0101 and data 1 and data 2
• 0110 or data1 nor data2
• 1000 add result data 1
• 1001 subtract result - data 1
• 1010 increment result 1
• 1011 decrement result - 1
• 1100 complement not result
• 1101 and result and data 1
• 1110 or result or data 1

10
Instruction Splitter

• This block splits the instruction set into
  the three parts of data1, data2 and op code

11
Splitter
BIST
Control Unit
RESET
go
digit
do
Instruction splitter
Register
ALU
Display Controller
opcode
opcode
carry
Data 1
borrow
Input
MUX
seg
Data 2
result
BIST
CLOCK
clock
Result to memory
12
Register
13
Register
BIST
BIST
Control Unit
Control Unit
opcode
input
input
go
seL
go
Reg_write
digit
digit
do
do
Instruction splitter
Register
ALU
Display Controller
Instruction splitter
Register
ALU
Display Controller
opcode
opcode
carry
RESET
RESET
Data 2
Data 1
Data 1
borrow
MUX
MUX
seg
seg
Data 1
Data 2
result
BIST
result
BIST
result
Data 2
CLOCK
clock
CLOCK
clock
Result to memory
14
Multiplexer

• Sends the output based on the select input
  received from Control Unit

15
Multiplexer
BIST
Control Unit
Sel-0
Sel-1
opcode
input
go
Reg_write
digit
do
Instruction splitter
Register
ALU
Display Controller
opcode
carry
RESET
Data 1
Data 1
borrow
MUX
seg
Data 2
result
BIST
result
Data 2
CLOCK
clock
Result to memory
16
Arithmetic Logic Unit
17
Arithmetic Logic Unit
BIST
Control Unit
input
opcode
go
digit
do
Instruction splitter
Register
ALU
Display Controller
opcode
Reg_out1
carry
RESET
MUX
MUX-out
- Sign
seg
BIST
result
CLOCK
clock
18
ALU

• Computes the result.
• Indicates the Carry or sign based on the
  operation result
• Output is zero when reset

19
Control Unit

• Sends operation codes to ALU
• Sends the required control codes to the
  Multiplexer and Memory based on the input opcode

20
Control Unit
BIST
Control Unit
input
O P C O D E
opcode
SEL
go
Reg_write
digit
do
Instruction splitter
Register
ALU
Display Controller
opcode
opcode
opcode
carry
RESET
borrow
MUX
seg
result
BIST
CLOCK
clock
21
Display Controller

• Accepts a 6-bit binary number between 0 and 63
  (output of the ALU)
• Converts binary number to a 2-digit BCD
  representation
• Generates appropriate logic levels to drive
  7-segment display

22
Display Controller
Digit-1
Digit-1
8
8
input
ALU
Display Controller
Result
Result
carry
go
8
8
Digit-2
Digit-2
- sign
do
8
result
RESET
Digit-3
- Sign
BIST
clock
CLOCK
23
Final Single Block Diagram
24
Simulation-Part1
25
Simulation-Part2
26
RTL Block Diagram
27
RTL Schematics-ALU
28
RTL Schematics-BCD Display
29
RTL Schematics-DisplayController
30
RTL Schematics-Instruction Set
31
RTL Schematics-MUX
32
RTL Schematics-Register
33
RTL Schematics-Splitter
34
Xilinx Layout
35
Xilinx FloorPlanner
36
Altera Layout
37
Flow Charts

• ALU Flow chart

38
Flow charts

• BCD Display

39
Flow charts

• Control Unit

40
Flow charts

• Display Controller

41
Flow charts

• Instruction Set

42
Flow charts

• MUX

43
Flow charts

• Registers

44
Flow charts

• Splitter

45
Block Diagram

• Left part of Block Diagram generated

46
Block diagram-2

• Right part of the block diagram

47
Single Block Diagram
48
Post Simulation

• Using Xilinx

49
Design Summary
50
Ucf File
51
Device Utilization Summary
Number of BUFGMUXs 3 out of 8
37 Number of External IOBs 29 out of
173 16 Number of LOCed IOBs 29
out of 29 100 Number of Slices
159 out of 1920 8 Number of
SLICEMs 0 out of 960
0
52
MIPS Processor
53
Scope for Development

• These cores can be mixed with add-in units such
  as SIMD systems, various input/output devices,
  etc.
• MIPS cores have been commercially successful, now
  being used in many consumer and industrial
  applications. MIPS cores can be found in newer
  Cisco and Linksys routers, cable modems and ADSL
  modems, smartcards, laser printer engines,
  set-top boxes, robots, handheld computers, Sony
  PlayStation 2 and Sony PlayStation Portable.

54
Summary and Conclusion

• This is an approximate basic sub part of a MIPS
  processor which is shown to work as a calculator
  which can be further developed into a ready to
  use core in MIPS architecture.

55
References

• 551 Homeworks and handouts
• www.Google.com
• http//en.wikipedia.org/wiki/MIPS_architecture