Memory Systems

1
Memory Systems

• Memory Hierarchy
• Memory Types
• Semiconductor Main Memory
• Interleaved Memory
• Associative Memory
• Cache Memory
• Virtual Memory

2
Semiconductor Main Memory

• Semiconductor Main Memory
• Memory Cell and Memory Unit
• Memory Organization
• Memory Design
• Example of a Commercial Memory Circuit
• Parameters of DRAM Memories
• Technologies for DRAM Memories

3
Parameters of DRAM Memories (1)

• Access time (tA) the time between the placement
  of the row address and the availability of the
  requested word
• Cycle time (tM) the minimum time between
  sequential read operations
• tM gt tA
• RAS Precharge time (tRP) the time needed to
  write back the memory contents and to activate
  the RAS signal

4
Parameters of DRAM Memories (2)

• Operations performed for a read access
• The processor sends the address of data
• The memory controller determines the row and
  column addresses of the data
• The memory controller sends the row address and
  asserts the RAS signal
• The row address decoder selects the row in which
  the data are stored, or reads the entire row and
  stores it in a buffer

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Parameters of DRAM Memories (3)

• Row Access time (tRA), also called access time
  (tA) or random access time the time between the
  assertion of the RAS signal and the selection of
  the row or the presence of data in the output
  buffer
• The memory controller sends the column address
  and asserts the CAS signal
• RAS-to-CAS delay (tRCD)

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Parameters of DRAM Memories (4)

• Column Access time (tCA) the time from the
  activation of the CAS signal after which the
  requested data will be available
• For synchronous memories the CAS latency (tCL) is
  used expressed as an integer number of clock
  cycles
• The selected data are sent from the output buffer
  to the data bus

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Parameters of DRAM Memories (5)

• Peak bandwidth of a DRAM module the amount of
  data transferred at maximum rate for a given
  memory bus configuration
• Ignores the initial time necessary to fetch the
  data from the DRAM module
• Sustained bandwidth takes into account an
  initial access to the memory, followed by a
  four-word transfer at the maximum rate

8
Parameters of DRAM Memories (6)

• Performance of a DRAM module can be expressed
  with the x-y-y-y designation
• Indicates the access time of the first word and
  the next three words (e.g. 5-2-2-2)
• Performance of a synchronous memory is indicated
  using the xyz designation
• tCL tRCD tRP
• Expressed in clock cycles (e.g. 222)
• The CAS latency can also be expressed as CL2
  (CAS2) or CL3 (CAS3)

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Page mode (1)

• If a sequence of memory accesses have the same
  row address it is sufficient to transfer the row
  address once
• An entire row of data (page) is read out and
  stored in an internal buffer ? page mode
• For a subsequent access to the same page, only a
  column address needs to be transferred
• There is no need to restore the page data at
  every access to a word

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Page mode (2)

• In page mode, the RAS signal is maintained active
  for the duration of a sequence of transfers
• The CAS signal is toggled in the normal way
• Page mode cycle time (tPC)
• For a memory with tRA 60 ns, a typical value is
  tPC 35 ns

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Four memory accesses in a row without page mode
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Four memory accesses in a row with page mode
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Semiconductor Main Memory

• Semiconductor Main Memory
• Memory Cell and Memory Unit
• Memory Organization
• Memory Design
• Example of a Commercial Memory Circuit
• Parameters of DRAM Memories
• Technologies for DRAM Memories

14
Technologies for DRAM Memories

• Technologies for DRAM Memories
• Categories of DRAM Memories
• SDRAM
• DDR SDRAM
• DDR2 SDRAM
• DDR3 SDRAM
• DDR4 SDRAM
• Memory Modules

15
Categories of DRAM Memories

• Almost all types of DRAM have the same initial
  latency to access the first word of memory (50
  .. 60 ns)
• Various techniques are used to perform the
  sequential read operations after the first word
  of memory is read
• Types of DRAM memories
• With asynchronous interface
• With synchronous interface
• Protocol-based

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DRAM Memories with Asynchronous Interface (1)

• The internal operations are assigned minimum time
  values
• If a clock pulse occurs prior to the minimum
  time, another clock pulse must occur ? the
  performance is limited
• Enhancing the performance increasing the number
  of bits per access overlapping various
  operations eliminating some operations

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DRAM Memories with Asynchronous Interface (2)

• Using wider I/O ports
• Additional I/O pins needed ? the cost increases
• The current drawn increases ? the speed is
  reduced
• Overlapping various operations
• Eliminating some internal operations
• FPM (Fast Page Mode)
• EDO (Extended Data Out)
• BEDO (Burst Extended Data Out)

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DRAM Memories with Synchronous Interface (1)

• The waiting periods for the processor are
  eliminated
• The DRAM latches some information from the
  processor under control of the system clock
  addresses, data, and control signals
• The system clock is the only timing signal that
  needs to be provided to the memory
• The inputs are simplified

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DRAM Memories with Synchronous Interface (2)

• DRAM memories with a synchronous interface SDRAM
• They are standardized by JEDEC (Joint Electron
  Device Engineering Council)
• PC133 SDRAM
• DDR SDRAM (Double Data Rate SDRAM)
• ESDRAM (Enhanced SDRAM)
• VCM (Virtual Channel Memory)
• FCRAM (Fast Cycle RAM)

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Protocol-based DRAM Memories

• The previous memory categories have separate
  address, data and control lines
• This may limit the operating speed
• Protocol-based DRAM memories implement the
  address, data, and control signals on the same
  high-speed bus
• Rambus DRAM
• SLDRAM (SyncLink DRAM)

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Technologies for DRAM Memories

• Technologies for DRAM Memories
• Categories of DRAM Memories
• SDRAM
• DDR SDRAM
• DDR2 SDRAM
• DDR3 SDRAM
• DDR4 SDRAM
• Memory Modules

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Principle of SDRAM Memory (1)

• Differences to the asynchronous DRAM
• Uses a multi-bank architecture (2 or 4 banks per
  module)
• Can operate in burst mode for 2 bits, 4 bits, 8
  bits, or a page
• The control method
• Synchronous DRAM is controlled by commands placed
  on the bus ? interpreted on the rising edge of
  the clock signal

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Principle of SDRAM Memory (2)

• The SPD chip (Serial Presence Detect)
• EEPROM memory included in the SDRAM module
• Contains information about the SDRAM module ?
  timing settings
• The speed of SDRAM memories
• Expressed in MHz
• The minimum clock cycle time (ns) is marked on
  the memory chips
• 10 fmax for the clock is 100 MHz

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Signals of an SDRAM memory (1)

• CLK (Clock)
• The rising edge of the clock signal initiates the
  command decoding and execution
• An SDRAM module uses 2 or 4 clock lines
• CKE (Clock Enable)
• Activates and deactivates the CLK signal
• When the CLK signal is deactivated, the input
  buffers are turned off to save power

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Signals of an SDRAM memory (2)

• CS (Chip Select)
• RAS, CAS, WE
• Same function as for asynchronous DRAM memories
• DQ (Data)
• DQM (DQ Mask)
• Used to control the data lines
• A (Address)
• BA (Bank Address)

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SDRAM Commands (1)

• An SDRAM command is determined by a combination
  of the CS, RAS, CAS, WE signals
• No Operation (NOP)
• Activates a memory chip and place it in the idle
  state
• Activate (ACT)
• Selects a particular memory bank and activates a
  row in the selected bank
• Read, Write

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SDRAM Commands (2)

• Read/Write with Auto Precharge
• Combine a read or write operation with an
  automatic precharge of an individual bank,
  without an explicit precharge command
• Advantage the precharge is performed at the
  earliest time within a burst transfer
• Execution of a Read with Auto Precharge command ?

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SDRAM Commands (3)
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SDRAM Commands (4)

• Burst Terminate
• Used to terminate burst transfers
• Precharge Selected Bank
• Indicates to the active memory bank to recharge
  itself in order to be ready for the next access
• Precharge All
• All banks are precharged at the same time

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SDRAM Commands (5)

• Auto Refresh
• Refreshes the SDRAM array explicitly
• Mode Register Set
• Loads the mode register with information on
• The burst length
• The CAS latency
• The order of accesses within a burst transfer

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Types of SDRAM Memories

• PC100
• Operating frequency 100 MHz
• Ideal timing 4-1-1-1
• Maximum bandwidth 8 x 100 x 106 B/s 800 MB/s
• PC150
• Operating frequency 150 MHz
• Maximum bandwidth 8 x 150 x 106 B/s 1200 MB/s

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Technologies for DRAM Memories

• Technologies for DRAM Memories
• Categories of DRAM Memories
• SDRAM
• DDR SDRAM
• DDR2 SDRAM
• DDR3 SDRAM
• DDR4 SDRAM
• Memory Modules

33
DDR SDRAM (1)

• DDR (Double Data Rate) SDRAM
• Data are transferred on both the rising and
  falling edges of the clock signal
• From proprietary versions of DDR memory, open
  specifications have been proposed, which are not
  protected by licenses
• The specifications have been standardized by the
  JEDEC committee in 2000

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DDR SDRAM (2)

• The interface transfers two data words at the I/O
  pins in each clock cycle
• A single 2nbit wide data transfer at the
  internal DRAM array
• Two nbit wide data transfers at the I/O pins
• A bidirectional data strobe (DQS)
• Transmitted along with the data
• Adjusts for variations in clock skew,
  capacitance, and interconnect length

35
DDR SDRAM (3)

• Read and write accesses are performed in burst
  mode
• The burst length can be programmed to 2, 4, or 8
  locations
• An Auto Precharge function may be enabled,
  initiated at the end of the burst access
• The CAS latency can be set to 2 or 2.5 clock
  cycles

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DDR SDRAM (4)

• Two types of applications module-based and
  component-based (point-to-point)
• Module-based applications main-memory systems
• Speed is limited by bus loading, line lengths
• Point-to-point applications graphics cards
• The DDR SDRAM chips are operating at 2.5 V ?
  power consumption is reduced by 25

37
DDR SDRAM (5)

• The DDR SDRAM types are named after their peak
  transfer rate
• PC2400 150 MHz, maximum transfer rate of 2,400
  MB/s
• In the JEDEC standard, the names used are based
  on the operating frequency
• DDR-300 DDR SDRAM performing data transfers at
  300 MHz (150-MHz clock)

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DDR SDRAM (6)
39
Technologies for DRAM Memories

• Technologies for DRAM Memories
• Categories of DRAM Memories
• SDRAM
• DDR SDRAM
• DDR2 SDRAM
• DDR3 SDRAM
• DDR4 SDRAM
• Memory Modules

40
DDR2 SDRAM (1)

• DDR2 SDRAM the second generation of DDR SDRAM
  memory devices
• The mass production of this memory began in 2003
• The data bus operates at twice the frequency of
  the memory cells ? 4 transfers in each clock
  cycle
• The operating voltage 1.8 V
• Increased pin count 240 compared to 184

41
DDR2 SDRAM (2)

• The initial frequency of data transfers
• 400 MHz for module-based applications (DDR2-400,
  PC2-3200)
• 800 MHz for point-to-point applications
  (DDR2-800, PC2-6400)
• The DDR2 specification also describes enhanced
  DDR modes at 400 MHz (3.2 GB/s) and 533 MHz (4.26
  GB/s)

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DDR2 SDRAM (3)

• Lower costs
• Implementing a fixed burst length (4 words)
• Elimination of ½ cycle latencies (e.g., 2.5)
• Elimination of the commands for interrupting
  transactions
• Increased latencies
• 3..9 clock cycles
• Higher bus speeds ? overall increased performance

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DDR2 SDRAM (4)
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Technologies for DRAM Memories

• Technologies for DRAM Memories
• Categories of DRAM Memories
• SDRAM
• DDR SDRAM
• DDR2 SDRAM
• DDR3 SDRAM
• DDR4 SDRAM
• Memory Modules

45
DDR3 SDRAM (1)

• DDR3 SDRAM the current DDR SDRAM memory
  generation
• Prototypes were announced in 2005
• The DDR3 standard has been published in 2007
• Chipset support in 2007 (Intel), 2008 (AMD)
• Reduced power consumption ? 40
• 90 nm fabrication technology
• Lower operating voltage (1.5 V)

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DDR3 SDRAM (2)

• Compatibility between DDR3 chipsets and DDR2
  memory modules
• Frequencies of data transfers between
• 800 MHz (DDR3-800, PC3-6400)
• 1600 MHz (DDR3-1600, PC3-12800)
• Advantages higher bandwidth, enhanced low power
  features
• Disadvantage higher CAS latency

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DDR3 SDRAM (3)
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Technologies for DRAM Memories

• Technologies for DRAM Memories
• Categories of DRAM Memories
• SDRAM
• DDR SDRAM
• DDR2 SDRAM
• DDR3 SDRAM
• DDR4 SDRAM
• Memory Modules

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DDR4 SDRAM

• DDR4 SDRAM the memory generation that will
  follow DDR3 SDRAM
• Frequency of data transfers
• 2.0 GHz (DDR4-2000, PC4-16000)
• 2.4 GHz (DDR4-2400, PC4-19200)
• 3.2 GHz (DDR4-3200, PC4-25600)
• Operating voltage 1.2 V
• Expected release 2011 or 2012

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Technologies for DRAM Memories

• Technologies for DRAM Memories
• Categories of DRAM Memories
• SDRAM
• DDR SDRAM
• DDR2 SDRAM
• DDR3 SDRAM
• DDR4 SDRAM
• Memory Modules

51
Memory Modules (1)

• DIMM (Dual In-Line Memory Module)
• Integrated memory circuits placed on a printed
  circuit board
• Separate electrical contacts on each side of the
  module (as opposed to SIMM)
• 64-bit datapath
• ECC (Error Correcting Code) DIMM performs error
  detection and correction
• SECDED (Single Error Correct, Double Error
  Detect) one additional bit for each byte

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Memory Modules (2)

• 168-pin DIMM for SDRAM
• 184-pin DIMM for DDR SDRAM
• 240-pin DIMM for DDR2 SDRAM and DDR3 SDRAM ? not
  compatible

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Memory Modules (3)

• SO-DIMM (Small Outline DIMM)
• Reduced size compared to DIMM modules
• Used for portable computers, networking devices
• 144-pin SO-DIMM for SDRAM
• 200-pin SO-DIMM for DDR SDRAM and DDR2 SDRAM
• 204-pin SO-DIMM for DDR3 SDRAM

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Memory Modules (4)

• 200-pin SO-DIMM module for DDR SDRAM
• (approx. 67 x 32 mm)

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Memory Modules (5)

• FB-DIMM (Fully Buffered DIMM)
• Communication between the memory controller and
  memory modules via a buffer AMB (Advanced Memory
  Buffer)
• AMB ? memory modules parallel interface
• Controller ? AMB and between memory modules two
  unidirectional point-to-point serial links

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Memory Modules (6)

• Synchronous packet-based serial communication
• Frequency 12 x the frequency of memory modules
• Advantages
• Simpler interconnections
• Higher data rates
• Larger number of memory modules
• Disadvantages
• Higher latency
• Higher power consumption

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Memory Modules (7)

• 240-pin FB-DIMM module for DDR2 SDRAM

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Questions

• What are RAS precharge time row access time
  CAS latency?
• What are the advantages of memories with
  synchronous interface?
• What are the differences between SDRAM and
  asynchronous DRAM memories?
• What are the main characteristics of DDR SDRAM
  memory?
• What are the improvements introduced by DDR2
  SDRAM memory?