A TimingDriven ModuleBased Chip Design Flow

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A Timing-Driven Module-Based Chip Design Flow
Fan Mo UC Berkeley Synplicity
Robert K. Brayton UC Berkeley
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Outline

• Design Flow and Timing Requirements
• Design Flows for Timing Closure
• Physical Synthesis Flow
• Module-Based Design Flow
• Comparison and Conclusion

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Timing Requirements
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A Timing-Driven Design Flow
Note Flattened design (one big module) may
contain huge number of internal paths.
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Physical Synthesis

• The accuracy of pre-synthesis.
• Module shapes and pin positions in floorplanning.
• The generation of the constraints.
• Delay distribution.

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The Module-Based Flow

• Versions of modules are flexibility generated in
  synthesis and used in physical design.
• The module generation does not depend on wiring
  prediction.

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The Module-Based Design Flow

• Two stages.
• Most iterations happen at the first stage.

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The Generation of Fast Version
Set the tightest constraints, which can never be
met. Nothing to estimate.

• Synthesis tool produces a module that is "as fast
  as possible".
• "Most friendly in timing" to other modules.

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The Generation of Slow Version 1
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The Generation of Slow Version
q is not based on wiring estimation. It is a
design input parameter (like area utilization in
SC placement). No delay distribution!
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The Integration of the Modules
Fishbone Block-Level Placement and Routing with
Buffer Insertion.
Using simple but predictable net topology.
Mo and Brayton, Fishbone A Block-Level Routing
Scheme, ISPD2003
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The Results
Physical Synthesis flow for comparison SIS
Silicon Ensemble On average, The Module-Based
flow achieves 13 shorter cycle than the Physical
Synthesis flow. And it is 77 faster.
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Case Study Comparing the Flows
Physical Synthesis flow
Module-Based flow
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Case Study Layout
Module-Based flow
Physical Synthesis flow
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What's Inside the Modules
Checkerboard module
Standard-cell module
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Conclusion

• Module-based design flow
• Regular logic structures and their synthesis
• Regular routing structure
• Future work
• New regular structures
• Noise-aware routing

Mo and Brayton, Regular Fabrics in Deep
Sub-Micron IC Design, Kluwer Academics, 2004