CSCE 211: Digital Logic Design

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CSCE 211Digital Logic Design

• Chin-Tser Huang
• huangct_at_cse.sc.edu
• University of South Carolina

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Chapter 6 Analysis of Sequential Systems
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Sequential System

• A system that has memory
• The output will depend not only on the present
  input but also on the past what has happened
  earlier
• Will focus on clocked systems (also called
  synchronous)

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Clock

• A signal that alternates between 0 and 1 at a
  regular rate
• The same clock is normally connected to all flip
  flops (a clocked binary storage device)
• The period of the signal is the length of one
  cycle the frequency is the inverse of the period
• In most synchronous systems, change occurs on the
  transition of the clock signal

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Conceptual View of a Sequential System
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A Continuing Example
CE6. A system with one input x and one output z
such that z 1 iff x has been 1 for at least
three consecutive clock times. State what is
stored in memory. It is stored in binary devices,
but the information to be stored is not always
naturally binary. Timing trace a set of values
for the input and output (and sometimes the state
or other variables of the system, as well) at
consecutive clock times.
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State Tables and Diagrams
State table shows for each input combination and
each state, what the output is and what the next
state is, that is, what is to be stored in memory
after the next clock.
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State Tables and Diagrams
State diagram (or state graph) a graphical
representation of the state table.
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State Tables and Diagrams
Mealy model the output depends not only on the
present state, but also on the present input.
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Latch

• A binary storage device, composed of two or more
  gates, with feedback

P (S Q) Q (R P)
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Gated Latch

• When Gate is 0, latch remains unchanged
• When Gate goes to 1, it behaves like the simpler
  latch

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Flip Flop

• A clocked binary storage device that stores
  either 0 or 1
• State of flip flop changes on the transition of
  the clock
• Trailing-edge triggered change takes place when
  the clock goes from 1 to 0
• Leading-edge triggered change takes place when
  the clock goes from 0 to 1

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Flip Flop

• What is stored after the transition depends on
  the data inputs and might also depend on what was
  stored in the flip flop prior to the transition
• Flip flops have one or two outputs
• State of the flip flop
• If there is a second output, it is the complement
  of the state

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D Flip Flop

• D means Delay
• Output is the input delayed until the next active
  clock transition
• Next state of D flip flop is the value of D
  before clock transition

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D Flip Flop
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Timing Diagram of D Flip Flop
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Two Flip Flops

• Connect the output of one flip flop to the input
  of another flip flop, and clock them
  simultaneously
• At a clock transition when the first flip flop q
  changes, the old value of q is used to compute
  the behavior of r

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Two Flip Flops
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Flip Flop with Clear and Preset
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Flip Flop with Clear and Preset
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T Flip Flop

• T means Toggle
• If input T is 1, the flip flop changes state
  (i.e. is toggled)
• If T is 0, the state remains the same

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T Flip Flop
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Timing Diagram of T Flip Flop
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JK Flip Flop

• JK is not an acronym of anything
• If J 0 and K 0 , the flip flop holds the
  current state
• If J 0 and K 1 , the flip flop resets q to 0
• If J 1 and K 0 , the flip flop sets q to 1
• If J 1 and K 1 , the flip flop changes its
  state

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JK Flip Flop
q Jq Kq
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Timing Diagram of JK Flip Flop
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Analysis Example 1
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D1 q1 q2 x q1 q1 D2 xq1 q2 z q2
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Analysis Example 1
D1 q1 q2 x q1 q1 D2 xq1 q2 z q2
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Analysis Example 2
JA x KA xB JB KB x A z A B
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Analysis Example 2
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Analysis Example 2
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Analysis Example 3
D1 xq1 xq2 D2 xq1q2 z xq1
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Analysis Example 3
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Analysis Example 3
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Analysis Example 4
Is this Moore model or Mealy model? Draw timing
diagram for input x 0 1 1 0 1 1 1 1 0
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Analysis Example 4