Memories I

1
Memories I

• Dr. T.Y. Chang
• NTHU EE
• 2005.10.18

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Contents

• SRAM
• DRAM
• Mask ROM, PROM, EPROM, and EEPROM
• Text Book D.A. Neamen, Electronic Circuits
  Analysis And Design, 2nd ed. Chapter 16.

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Memories Classifications

• Random Access Memories (RAMs)
• Volatile lose data when power off
• Search
• Content-Addressable Memories (CAMs)
• Store data
• Static RAM (SRAM)
• Faster, 6 Trs/cell
• Dynamic RAM (DRAM)
• High Density, 1 Tr and 1C per cell, need refresh

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Memories Classifications

• Read-Only Memories (ROMs)
• Nonvolatile retain data even power off
• Store OS, fixed data
• Field Programmable Memories
• Nonvolatile
• EPROM, EEPROM, FPGA, Flash, FRAM

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Memory Architecture

• Inputs Address lines, Data line(s), R/W control,
  Enable (Optional)
• Output data line(s)

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RAM Architecture

• Decoder N address lines decode to 2N lines with
  only one selected
• Memory array
• Control circuit

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Decoder Using NAND or NOR
(a4a3a2a1a0) a4a3a2a1a0 (00101)
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SRAM Cells NMOS
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Example 16.15 _at_1080

• Determine currents, voltages, and power
  dissipations in depletion-load and resistor-load
  NMOS SRAM cells with parameters listed below
  VDD3V, RD2M?, (W/L)D2, (W/L)L1/2, VTND0.5V,
  VTNL?1V, and kn60uA/V2.

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CMOS SRAM Cell
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CMOS SRAM Cell with pull-up
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Read Operation

• IMNA(S)ltIMN1(NS) (IMNB(S)ltIMN2(NS))
• KnA(VDD?Q?VTN)2ltKN12( VDD ?VTN )Q ?Q2 QVTN
• (W/L)nA/(W/L)n1lt 2(VDD VTN) ?3V2TN /(VDD ?2VTN
  )2
• VDD 3, VTN 0.5
• (W/L)nA/(W/L)n1lt0.56

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Write Operation

• IMp2(S)ltIMNB(NS) (IMP1(S)ltIMNA(NS))
• Kp2(VDDVTP)2ltKNB2( VDD ?VTN )Q ?Q2 QVTN
• (W/L)p2/(W/L)nBlt (kn/kp)2(VDDVTN)?3V2TN /(VDD
  VTp )2
• VDD 3, VTN 0.5, VTP ? 0.5, then
  (W/L)p2/(W/L)nBlt0.72

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SRAM R/W Circuitry
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Write
16
DRAM Cell

• Logic-0 0 V
• Logic-1 VDD ? VTN

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DRAM Operations

• Dummy Cell CR0.5 CS
• Init VCR0, ?21 Precharge, CEbar1
• Read ?20, CEbar0, charge redistrib.
  D-WLRowSel WL1
• R0 V1ltV2
• R1 V1gtV2

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ROM

• Mask ROM
• Select Y
• Select X
• Q ? Vo0
• No Q ? Vo1

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Programmable ROM

• Blow fuses by user
• Select X
• Select Y
• Vo 0 fuse exits
• Vo 1 No fuse

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EPROM
21
EPROM Program and Erase
Ref. Book D.A. Hodges, H. G. Jackson, R. A.
Saleh, "Analysis and Design of Digital
Integrated Circuits," 3rd Ed., McGraw Hill,
2004. Chapter 9.
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EEPROM
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Problems

• For a 1Mx1 RAM, how many address lines are
  required?
• P16.72 Design a 4-word ? 4-bit NMOS Mask ROM to
  produce output of 1011, 1111, 0110, and 1001 when
  rows 1, 2, 3, and 4, respectively are addressed.

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Solutions

• 1M220, and the number of address lines required
  is 20.
• See figure below