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Title: Electronics Status


1
Electronics Status
  • Philippe Farthouat
  • CERN
  • ATLAS Plenary June 25, 2004

2
Outline
  • Production of ASICs
  • Production of Front-end Systems
  • Production of Back-end Systems
  • Production of Power Supplies
  • TTC issues
  • Radiation hard electronics
  • Infrastructure
  • EMC in ATLAS
  • Next developments
  • Summary

3
Production of ASICs
4
Production of ASICs (cont)
5
Production of ASICs. Comments
  • All ATMEL (DMILL) wafers have been delivered
  • TRT ASDBLR
  • 55 parametric yield (Enough for the complete
    detector)
  • Test injection capacitor failures observed
  • LArg wafers
  • Good yield for all the chips
  • Dispute with ATMEL not yet finished but out of
    our control
  • Two ASICs on the critical path
  • RPC CMA which required a major redesign because
    of a change in the RPC cable lengths (input
    adjustment pipeline too short)
  • Submitted now and expected end of the year
  • TGC Slave Board ASIC (SLB)
  • Last iteration received this summer needs a fix.
    Resubmitted and expected this month

6
Front-end Systems (1)
  • All systems are either in full production or
    starting it
  • PRR done for most of them
  • To be noticed
  • Liquid Argon Calorimeter
  • 58 Front-end crates
  • More than 2000 custom boards
  • Very complex boards (in particular the FEB)
  • Tile Calorimeter
  • Production to be finished before next March
  • MDT Chambers
  • All the mezzanine boards produced

7
Front-End Systems (2)
  • TRT
  • Barrel front-end boards
  • Available for all barrel modules
  • 14 layers with buried vias
  • fpBGA on both sides
  • End-cap front-end boards
  • Pre-production on-going

8
Front-End Systems (3)
  • Test stand of the LArg FEB

9
Back-end Electronics (ROD)
  • Pixel-SCT PRR passed
  • Production to start now
  • TRT full scale prototype available
  • Successfully used in the test beam
  • Change in the read-out granularity to be done to
    allow a complete staging of the C-Wheels
    electronics
  • Double-density ROD to save money

10
Back-end Electronics (ROD)
  • LARG/Tile
  • PRR done
  • MDT ROD
  • On-going redesign based on FPGA SHARC
  • Design finished
  • Lay-out to be done
  • Expected prototype end of this year

11
Power Supplies (1)
  • Radiation hard STm Voltage regulators
  • Positive and Negative versions available
  • Available through CERN store
  • Last negative version not yet delivered
  • CERN store enquiring
  • 2004 should have been the last year to order
    these components. Well still be able to order
    next year

12
Power Supplies (2)
  • Pixel
  • Power supplies (LV and HV) in USA15 and US15
  • ST regulators at patch panel 2 level
  • FDR last June
  • Commercial devices
  • Good candidates for LV and HV from WIENER, CAEN
    and ISEG
  • SCT
  • Power supplies in USA15 and US15
  • Production on-going
  • HV modules in Krakow (problem with a failure mode
    being fixed)
  • LV modules in Prague
  • TRT
  • LV in UX
  • Good candidates from Wiener or CAEN
  • Tendering process started Market survey done
    and tender to be issued soon (by PH-ESS)
  • HV in USA15
  • Price enquiry out soon to about 10 companies
  • Several candidates (CAEN, Dubna, ISEG)

13
Power Supplies (3)
  • LArg LV
  • DC-DC converters close to the calorimeter
  • 280V DC input
  • 250 kW total
  • Production starting
  • End in July 2005
  • Very long development to obtain a device
    sufficiently radiation-hard
  • LArg HV
  • Power supplies from ISEG
  • Production done
  • A problem with broken capacitors being
    investigated

14
Power Supplies (4)
  • Tile HV
  • Bulk supply and distributor in the drawers
  • Production on-going
  • Tile LV
  • DC-DC in the fingers
  • Design finalised
  • A few boxes in production
  • Still some radiation tests to be done
  • PRR expected late fall
  • Muon System
  • Same scheme for all chambers
  • Commercial power supplies in UX15
  • CAEN and Wiener are very good candidates
  • Granularity adapted to the cost
  • Several chambers/layers per power supply (both HV
    and LV)
  • Tender in preparation

15
TTC Issues
TiTiSee
16
TTC issues
  • TTC components in the pit
  • It is the responsibility of level-1 team to
    provide (and pay for) to each system the TTC
    components from the TTCvis up to the end of the
    fibres
  • TTCvi, TTCxx, Fibres, TTCoc
  • It is responsibility of level-1 to provide to
    each system the pin diodes, TTCrx and QPLL. These
    devices are paid by the systems
  • TTCrx, Pin diodes available (56 ChF and 9 ChF)
  • TTC components for test systems
  • Test beam, commissioning stands, lab set-up
  • Requests through the electronics co-ordinators
  • Each sub-system should have given its needs about
    a year ago
  • Some needs are not yet covered
  • Last order of components

17
QPLL Problems (1)
  • Because of the protocol used by the TTC, the
    extracted clock at the receiving end (TTCrx) has
    some jitter
  • 30 100 ps rms depending on traffic on the
    B-Channel
  • This jitter is too high for the Gbit link
    serialisers or some LVDS serialisers
  • QPLL is a PLL driven by a crystal oscillator and
    it filters the jitter on the clock delivered by
    the TTCrx
  • Jitter less than 100 ps peak-to-peak
  • It recently appeared that in about 25 of the
    cases a huge jitter (3 ns) appears at certain
    frequency and/or temperature
  • Low frequency drift ? does not disturb the Gbit
    Links
  • Destroys any timing measurement
  • Very serious problem for the ATLAS LArg
  • So far only ATLAS LArg has reported on this
    problem

18
QPLL Problems (2)
Bad one
Good one
19
QPLL Problems (3)
  • On-going effort to try and understand this
    problem
  • Extensive measurements made by the engineer in
    charge of the TTC with the help of Stefan Simion
    (LArg)
  • Two engineers in the CERN MIC group running
    extensive simulation and trying different
    solutions
  • Quite a lot of power injected in the crystal
  • Addition of extra capacitance or resistance cure
    the problems but
  • Addition of a sufficiently high value resistor
    increases the high frequency jitter at a level
    which could disturb the Gbit Links
  • Addition of capacitors reduces the working
    frequency range (still OK for us)
  • An engineer from the company which delivered the
    crystals is investigating
  • No results yet and interaction a bit slow
  • LArg (Nevis) has contacted another company
  • Samples measured at CERN with QPLL. All (almost)
    OK (only 3 devices measured)
  • Problem to be solved asap as it blocks the LArg
    front-end boards production

20
Radiation Hardness (1)
Report from Francis Anghinolfi
  • Components pre-selection ? 99 achieved
  • Missing
  • Some Pixel and TRT PP2 electronics
  • One FPGA on MDT CSM Board
  • RPC Coincidence Matrix (ASIC)
  • Production qualification ? 72 achieved
  • Missing
  • Pixel Production going on
  • TRT PP2
  • LArg Optolink
  • MDT CSM
  • EC MDT Alignment
  • TGC 50 production
  • RPC 50 production

Fully Completed - SCT - CSC - TILE CAL - Barrel
MDT Alignment
21
Radiation Hardness (2)
  • Power Supplies
  • All components pre-selection achieved
  • No production phase presently started up
  • LARG PS PRR done 2 pre-series units Nov04
  • TILE CAL PRR Q404
  • Muon LV/HV commercial devices
  • Validation of the production to be organised

22
Radiation Hardness (3)
  • We should be careful about qualification of Power
    Supplies (schedule)
  • It appears some late electronics developments
  • E.g. Pixel and TRT PP2 boxes
  • Single component added at the last minute on PCB
    should be identified
  • E.g. protection devices
  • Verification Process during installation or
    commissioning (incl. safety/monitoring devices,
    crane control, cooling/cryogenics control, etc )
    to be defined

23
Infrastructure
Report from Georges Blanchot
  • USA15. Levels 1 and 2, transformers and
    switchboards
  • 250 racks are in place, ready to receive power
    and equipment
  • Power distributed with CANALIS bus-bars 800A
    (500 kW) primary, 160A (170 kW) secondary
  • On the critical path now
  • UX15. HS structures, levels 0 to 8
  • Need to specify power requirements and to update
    the EMDH database
  • First round with responsibles of racks done
  • Standard switchboards and cabling
  • Not on the critical path now

24
Power to Racks in USA15
  • The power distribution is made of
  • Canalis busbars
  • Carry the power to the rack
  • Control bus
  • Control bus to communicate with the Twido box
  • Twido box
  • On/Off and other monitoring functions with a
    TWIDO PLC connected to control bus
  • Distribution Box
  • 3 plugs for racks, mono or triphased versions,
    with remote control of the switch
  • 1 auxiliary plug
  • 1 plug for ventilation unit

25
USA15 Racks Room
  • Where required, temporary plugs will be
    supplied ASS on level 2, DCS on level 1. General
    services plugs are already in place
  • Some racks require UPS/Diesel, installed at a
    later stage. Must run on temporary plugs DCS,
    DSS, ASS
  • First branch to get power level 1, 4 rows,
    including Tilecal, end october
  • Once working, all other branches to be installed
  • Next milestone LArg needs its racks in February
    05
  • Cooling parts (turbines, deflectors, heat
    exchangers) january 2005

26
UX15 Racks
  • Need to define power requirements.
  • Need to form power groups of racks.
  • Too little information on EMDH first round of
    enquiries done by email.

27
Summary Infrastructure
  • Electrical distribution to USA15 in progress
  • Power is delivered on the basis of data available
    in EMDH
  • ? System must make sure this is up to date
  • Tilecal to get power by end october
  • ? Others by end november
  • Cooling parts ordered and to be delivered (and
    installed) in January 05
  • Confirm power needs for racks in UX15
  • Rack configuration in EMDH too
  • ? Systems must fill in the Rack Wizard database
    here also
  • Preliminary data available

28
ATLAS EMC Policy
Reference document is available
at https//edms.cern.ch/file/476490/1/ATLAS-EMC-P
OLICY.pdf Additional Information is available
at http//atlas.web.cern.ch/Atlas/GROUPS/FRONTEND
/EMC/
  • EMC Procedures in ATLAS
  • Safety and Installation Report.? The setup must
    in all cases comply with the CERN safety rules.
  • EMC Report.? The required noise performance must
    be achieved.? The system must not be a
    disturbance for other systems.
  • Commissioning.? Insure that installlation is
    done as defined in steps 1 and 2.

29
EMC Issues Specific to ATLAS
  • Grounding
  • Large dimensions of the experiment ? long
    grounding wires
  • Ground wire is a safety requirement
  • Difficult to insure equipotentiality between
    detectors and their racks located 100 meter away
  • Common mode noise
  • Results from the long cables and limited ground
    equipotentiality
  • Common mode noise radiates more than 103 times
    than differential mode noise
  • Noise coupling mainly caused by CM emissions of
    cables
  • Power cables to switched mode power supplies and
    other power equipment (motors, pumps)
  • Digital transmission (fast transients) copper
    links, such as fieldbuses, serial buses, relays
  • Near field
  • Couplings mostly to happen in the near field
    region inside cable trays
  • Distinguish electric (capacitive) and magnetic
    (induction) near field couplings
  • Type of coupling conditions the type of shielding
    requirement
  • Long Conductors
  • Results in CM/DM conversions along the cable
    (multiconductor transmission lines analysis)
  • Results in noise amplification and attenuation
    for given frequencies.
  • Capacitive couplings between systems
  • Electrically isolated detectors share large
    surface gaps capacitive coupling used by CM
    currents.

30
Measurements CM Emissions
31
Measurements Immunity
32
EMC Summary
  • ATLAS EMC Policy
  • Quality and risk management issue
  • Establishes methods and procedures to insure the
    systems electromagnetic compatibility in the
    experiment environment
  • Compliance requirements specific to the ATLAS and
    CERN environments
  • Procedures
  • Clear description of the setup
  • To insure compliance with safety rules
  • First document from LArg in approval process
  • To define the valid configuration for EMC
    measurements
  • EMC Measurements
  • Specific for each system
  • Started this summer (MDT in H8, Tile Cal)
  • To understand how noise couples into a system and
    affects its performance, within the established
    compatibility limit
  • Guidelines
  • On grounding configurations, coupling modes,
    cable shields, shield terminations routing
    paths, test methods, tools

33
Future developments
  • Although still very early, future developments
    for LHC upgrades have to be considered
  • Main points to be looked at
  • Which technology(ies) could be used
  • Power management
  • Does not aim at being a complete study of the
    situation but at pointing potential problems
    which may influence our working habits
  • Most of the material presented from Sandro
    Marchioro

34
Technologies
  • One of the possibilities is to continue very good
    relations with DSM vendors and to start looking
    at CMOS very deep sub-micron technologies
  • 130 or 90 nm
  • First evaluation of 130 nm shows that the
    radiation hardness is very good
  • Linear transistors look very promising with minor
    weaknesses
  • No guard-ring needed
  • Sensitive charge smaller, higher SEU sensitivity
  • NB without enclosed transistors, error rates can
    be considerably higher than for present 0.25mm
    designs
  • Latch-up not observed and not expected to be a
    issue
  • However there are difficulties

35
Cost
  • We clearly cannot afford hundreds of
    developments and prototypes

36
Developments in 0.25µ
37
Cost comparison
From Sandro Marchioro
Assuming one iteration and ABCD type chip
  • Clearly points towards
  • Very few different designs produced in large
    quantity
  • A single iteration

38
Power
  • These technologies leak
  • Without careful design the power will not
    decreased
  • Nor the current (Vdd is going down)

39
Future Developments
  • Cost of the new technologies will force us to
    co-ordinate the efforts
  • Whatever the choice is, the power and the way of
    getting it inside the detector volume is a major
    problem which requires RD
  • Not mentioned was the complexity (and cost) of
    the design tools
  • Requires training and practice
  • The existing expertise among the different
    institutes must be maintained

40
Summary
  • Front-end ASICs
  • All are produced except
  • Pixel FEI which is still in production (no
    problems)
  • CMA from the RPC which has just been submitted
  • SLB from TGC which needed a fix
  • Front-end systems
  • All in production
  • Several systems have started the
    production/procurement of power supplies
  • Solutions exist for the others (Pixels, TRT,
    Muons)
  • Radiation hardness validation not to be forgotten
  • Radiation hard electronics
  • Be careful that nothing is forgotten during
    installation
  • EMC policy (Grounding and shielding) to be applied
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