Resource Budgeting for Multiprocess Highlevel Synthesis

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Resource Budgeting for Multiprocess High-level
Synthesis

• Weidong Wang Raghunathan, A. Jha, N.K. Dey,
  S.Computer-Aided Design of Integrated Circuits
  and Systems, IEEE Transactions onVolume 23, 
  Issue 7,  July 2004 Page(s)1010 1019
• Presenter hyChen

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Outline

• Abstract
• Introduction
• Relate Work
• Methodology
• Experimental Result
• Conclusion

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Abstract

• AbstractThis paper presents a new high-level
  synthesis methodology to generate optimized
  register-transfer level (RTL implementations for
  multiprocess behavioral descriptions. The
  concurrent communicating processes specification
  paradigm is widely used in digital circuit and
  system design, and is employed in all popular
  hardware description languages. It has been shown
  that interprocess communication and
  synchronization can result in complex timing
  interdependencies, which significantly affect the
  performance of a multiprocess system.
• In this paper, we demonstrate that
  state-of-the-art high-level synthesis tools can
  generate significantly suboptimal implementations
  for behaviors that contain concurrent
  communicating processes. We present an analysis
  of how interprocess communication impacts
  high-level synthesis steps, and describe a new
  methodology to adapt existing high-level
  synthesis tools to optimize multiprocess
  descriptions. Our methodology is based on
  executing multiprocess performance analysis and
  process-by-process scheduling in an iterative
  manner. We present algorithms for key steps in
  the proposed methodology.

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Abstract-cont.

• We have performed extensive experiments in the
  context of a commercial high-level design flow to
  evaluate the proposed techniques. The results
  clearly demonstrate the utility of our techniques
  in synthesizing implementations with superior
  area, performance, and energy consumption. For
  example, up to 40.0 performance improvement
  (average of 35.6) was achieved with little or no
  area overhead (average of 4.8). In effect, the
  proposed techniques lead to a shift of the entire
  area-delay tradeoff curve for a design, to
  include superior designs that were hitherto
  infeasible. Our techniques also simultaneously
  result in up to 50.0 (average of 33.5)
  improvement in energy and up to 69.0 (average of
  58.3) improvement in the energy-delay product.
  

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Introduction

• High-Level synthesis is an extensively researched
  field.
• All research in high-level synthesis have focused
  on synthesis of behavioral descriptions that
  contain a single process.
• Whats the problem?
• A multiprocess system is handled by synthesizing
  each process separately into an RTL
  implementation.

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Relate Work

• 1213
• Correct synchronization in multiprocess high
  level synthesis.
• 1415
• A process graph analyzer for multiprocess.
• 1617
• A worst case performance analysis for
  multiprocess.

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Example Control Flow Graph for Ethernet
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Example Different Resource budgets

• Global resource adder(6), bit-operator(3),
  comparator(7)
• Equal vs. Operation Count vs. Papers method

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Example-Method

• Budget the resources to each process
• Operations which appear in the critical path as
  well as near-critical paths.
• The critical path can change after resource
  budgeting and rescheduling.

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Methodology for High-level Synthesis
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Methodology (cont.)

• Performance Analysis
• Using simulation-based.
• Criticality Calculation
• Operations which appear in the critical path as
  well as near-critical paths.
• e-critical path L(p)
• L(p) gt (1-e)L0, 0 ltelt 1
• State transition graph (STG)
• Generated from using the testbench to resolve the
  execution of branches and loops.

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Methodology-Pseudocode
Depth-first search
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Methodology-STG
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Methodology (cont.)

• Criticality Driven Resource Budgeting
• Rel_Res_Reqi,j (each process)
• 1 ?k1,OPk?i criticality (OPk)
• i process, j resource type
• Rel_Res_Reqj (total process)
• ?i1 Rel_Res_Reqi,j
• Ri,j (Resource Budgeting)
• Ri,j each process/ total process (Resj)

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Methodology-Discussion

• Clock selection
• Different processes can use different clocks.
• Synchronizing signals vs. Data signals
• No discussion about Data signals.

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Experimental-Benchmarks

• Behavior to High-level synthesis Cyber
• Logic synthesis to physical Synopsys Design
  Comiper
• NECs .35 cell-based array library

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Experimental Results - Area and Performance
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Experimental Results Energy
Average reduce 33.5
58.3
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Experimental-tradeoff curve

• Original the better result chosen from equal
  distribution and operation count based
  distribution

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Conclusion

• Concurrent communicating processes are widely
  used as a behavioral hardware specification
  paradigm.
• Developed a methodology to optimize multiprocess
  designs during high-level synthesis.