IR

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(No Transcript)
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Multicycle Implementation
IR
MDR
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State Register Transfers
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9 S S2 A
sign_ext(IR15-0) ALUOut,
LWS3 SWS5
S S3 M ALUOut MDR, S4 S S4
MDR R IR20-16, S0 S S5 B
M ALUOut, S0 S S6 A op B
ALUOut, S7 S S7 ALUOut
RIR15-11, S0 S S8 Zero PC Zero
ALUOut PC, S0 S S9 PC31-28
shlt2(IR25-0) PC, S0 S
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Control Logic Summary Blanks are Dont Cares
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 RegDst
0
1 MemtoReg
1
0 RegWrite 0 0 0 0 1
0 0 1 0 0 MemRead
1 0 0 1 0 0 0 0 0
0 MemWrite 0 0 0 0 0
1 0 0 0 0 IorD
0 1 1 IRWrite
1 0 0 0 0 0 0
0 0 0 PCWrite 1 0 0
0 0 0 0 0 0 1 PCWriteCond
0 0 0 0 0 0 0
1 PCSource 00
01 10 ALUSrcA
0 0 1 1
1 ALUSrcB 01 11 10
00 00 ALUOp 00
00 00 10 01
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State Register Transfers
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9 S S2 A
sign_ext(IR15-0) ALUOut,
LWS3 SWS5
S S3 M ALUOut MDR, S4 S S4
MDR R IR20-16, S0 S S5 B
M ALUOut, S0 S S6 A op B
ALUOut, S7 S S7 ALUOut
RIR15-11, S0 S S8 Zero PC Zero
ALUOut PC, S0 S S9 PC31-28
shlt2(IR25-0) PC, S0 S
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State Diagram
S0
Start
S1
j
beq
lwsw
R
S2
S6
S8
S9
lw
sw
S3
S5
S7
S4
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MIPS Lite Control Unit
Input
NS0 NS1 NS2 NS3
Op0 Op1 Op5
S0 S1 S2 S3
Combinational Logic
Register S
Clock
Output
16 Control Signals
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Make State Assignments Use decimal
equivalent Inputs S3, S2, S1, S0, Op5, Op4, Op3,
Op2, Op1, Op0 Next State NS3, NS2, NS1, NS0
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Make State Assignments Use decimal
equivalent Inputs S3, S2, S1, S0, Op5, Op4, Op3,
Op2, Op1, Op0 Next State NS3, NS2, NS1,
NS0 Consider NS1 NS1 1 for Next State 2 Next
State 3 Next State 6 Next State 7
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
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State Diagram
S0
Start
S1
j
beq
lwsw
R
S2
S6
S8
S9
lw
sw
S3
S5
S7
S4
See Appendix C Mapping Control to Hardware
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Make State Assignments Use decimal
equivalent Inputs S3, S2, S1, S0, Op5, Op4, Op3,
Op2, Op1, Op0 Next State NS3, NS2, NS1,
NS0 Consider NS1 NS1 1 for Next State 2
S3, S2, S1, S0 (Op5, Op4, Op3, Op2, Op1, Op0
Op5, Op4, Op3, Op2, Op1, Op0) Next State
3 Next State 6 Next State 7
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State Diagram
S0
Start
S1
j
beq
lwsw
R
S2
S6
S8
S9
lw
sw
S3
S5
S7
S4
See Appendix C Mapping Control to Hardware
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Make State Assignments Use decimal
equivalent Inputs S3, S2, S1, S0, Op5, Op4, Op3,
Op2, Op1, Op0 Next State NS3, NS2, NS1,
NS0 Consider NS1 NS1 1 for Next State 2
S3, S2, S1, S0 (Op5, Op4, Op3, Op2, Op1, Op0
Op5, Op4, Op3, Op2, Op1, Op0) Next State
3 S3, S2, S1, S0 (Op5, Op4, Op3, Op2, Op1, Op0
) Next State 6 Next State 7 NS1 Logical sum
of above
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State Diagram
S0
Start
S1
j
beq
lwsw
R
S2
S6
S8
S9
lw
sw
S3
S5
S7
S4
See Appendix C Mapping Control to Hardware
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Make State Assignments Use decimal
equivalent Inputs S3, S2, S1, S0, Op5, Op4, Op3,
Op2, Op1, Op0 Next State NS3, NS2, NS1,
NS0 Consider NS1 NS1 1 for Next State 2
S3, S2, S1, S0 (Op5, Op4, Op3, Op2, Op1, Op0
Op5, Op4, Op3, Op2, Op1, Op0) Next State
3 S3, S2, S1, S0 (Op5, Op4, Op3, Op2, Op1, Op0
) Next State 6 S3, S2, S1, S0 (Op5, Op4, Op3,
Op2, Op1, Op0 ) Next State 7 NS1 Logical
sum of above
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State Diagram
S0
Start
S1
j
beq
lwsw
R
S2
S6
S8
S9
lw
sw
S3
S5
S7
S4
See Appendix C Mapping Control to Hardware
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Make State Assignments Use decimal
equivalent Inputs S3, S2, S1, S0, Op5, Op4, Op3,
Op2, Op1, Op0 Next State NS3, NS2, NS1,
NS0 Consider NS1 NS1 1 for Next State 2
S3, S2, S1, S0 (Op5, Op4, Op3, Op2, Op1, Op0
Op5, Op4, Op3, Op2, Op1, Op0) Next State
3 S3, S2, S1, S0 (Op5, Op4, Op3, Op2, Op1, Op0
) Next State 6 S3, S2, S1, S0 (Op5, Op4, Op3,
Op2, Op1, Op0 ) Next State 7 S3, S2, S1, S0
NS1 Logical sum of above
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MIPS Lite Control Unit
Input
NS0 NS1 NS2 NS3
Op0 Op1 Op5
S0 S1 S2 S3
Combinational Logic
Register S
Clock
Output
16 Control Signals
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Control Logic Summary Blanks are Dont Cares
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 RegDst
0
1 MemtoReg
1
0 RegWrite 0 0 0 0 1
0 0 1 0 0 MemRead
1 0 0 1 0 0 0 0 0
0 MemWrite 0 0 0 0 0
1 0 0 0 0 IorD
0 1 1 IRWrite
1 0 0 0 0 0 0 0
0 0 PCWrite 1 0 0
0 0 0 0 0 0 1 PCWriteCond
0 0 0 0 0 0 0
1 PCSource 00
01 10 ALUSrcA
0 0 1 1
1 ALUSrcB 01 11 10
00 00 ALUOp 00
00 00 10 01
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S1 S0
00 01 11 10
00 01 11 10
0 1 1
S3 S2
IorD
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S1 S0
00 01 11 10
00 01 11 10
0 1 1
S3 S2
IorD S0
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MIPS Lite Control Unit
Input
NS0 NS1 NS2 NS3
Op0 Op1 Op5
S0 S1 S2 S3
Combinational Logic
Register S
Clock
Output
16 Control Signals
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ROM (or PROM) Approach Read Only Memory
01 . . . 011
Output Om,. . .O2, O1
Address An, . . . A2,A1
m outputs
n inputs 2n entries
No dont cares
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ROM (or PROM) Approach Read Only Memory
Inputs S3, S2, S1, S0, Op5, Op4, Op3, Op2, Op1,
Op0
01 . . . 011
Outputs NS3, NS2, NS1, NS0 16 Control
lines Total 20 bits
10 inputs
16 Control Lines
NS 3 -0
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Input
NS0 NS1 NS2 NS3
Op0 Op1 Op5
S0 S1 S2 S3
ROM 210 x 20
Register S
Clock
Output
16 Control Signals
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Input
Op0 Op1 Op5
NS0 NS1 NS2 NS3
S0 S1 S2 S3
ROM 24 x 16
ROM 210 x 4
Clock
16 Control Lines
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Input
Op0 Op1 Op5
NS0 NS1 NS2 NS3
S0 S1 S2 S3
ROM 24 x 16
ROM 210 x 4
Clock
16 Control Lines
Previous was 210 x 20 20K bits Now 4K 256
bits
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PLA Approach Programmable Logic Array
A1 A2 An
.. .. .. ..
ooo o oo o o o
o
OR Plane
AND Plane
...
O1 O2 Om

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PLA Approach Programmable Logic Array
A1 A2 An
O1 O2 O3 Om
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PLA Approach Programmable Logic Array
See Fig C.14 page C-20 For PLA Implementation
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State Diagram
S0
Start
S1
j
beq
lwsw
R
S2
S6
S8
S9
lw
sw
S3
S5
S7
S4
Pattern of Sequential States
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Next State Function with a Sequencer
16 Control Lines
ROM PLA
AddrCtl
1
STATE
Adder
Addr Select logic
Op(5 0)
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State Diagram
S0
Start
S1
j
beq
lwsw
R
S2
S6
S8
S9
lw
sw
S3
S5
S7
S4
Pattern of Sequential States
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Next State Function with a Sequencer
16 Control Lines
ROM PLA
AddrCtl 0 - Set to 0 1 Dispatch ROM1 2
Dispatch ROM2 3 Use Incremented State
1
STATE
Adder
Addr Select logic
Op(5 0)
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ROM
AddrCtl
1
STATE
Adder
3 2 1 0
0
Dispatch ROM 2
Dispatch ROM 1
Op(5-0)
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Control Logic Summary Blanks are Dont Cares
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 RegDst
0
1 MemtoReg
1
0 RegWrite 0 0 0 0 1
0 0 1 0 0 MemRead
1 0 0 1 0 0 0 0 0
0 MemWrite 0 0 0 0 0
1 0 0 0 0 IorD
0 1 1 IRWrite
1 0 0 0 0 0 0
0 0 0 PCWrite 1 0 0
0 0 0 0 0 0 1 PCWriteCond
0 0 0 0 0 0 0
1 PCSource 00
01 10 ALUSrcA
0 0 1 1
1 ALUSrcB 01 11 10
00 00 ALUOp 00
00 00 10 01
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State Diagram
S0
Start
S1
j
beq
lwsw
R
S2
S6
S8
S9
lw
sw
S3
S5
S7
S4
Pattern of Sequential States
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Control Logic Summary Blanks are Dont Cares
S0 S1 S2 S3 S4 S5 S6 S7 S8
S9 AddrCtl 00 0 0 0 0 1 1
0 1 1 1 01 0 1 0 0 0
0 0 0 0 0 10 0 0 1
0 0 0 0 0 0 0 11 1 0
0 1 0 0 1 0 0 0
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S1 RIR25-21 A, RIR20-16 B,
PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9 S
Dispatch ROM 1 Address Contents
Op NS R-type 000000 0110 j 00
0010 1001 beq 000100 1000 lw 100011 0010 sw 101
011 0010
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S2 A sign_ext(IR15-0) ALUOut,
LWS3
SWS5 S
Dispatch ROM 2 Address Contents
Op NS lw 100011 0011 sw 1010
11 0101
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Next State Function with a Sequencer
16 Control Lines
ROM PLA
AddrCtl
1
STATE
Adder
Addr Select logic
Op(5 0)
Looks like a Computer !
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Exceptions are unexpected or error events. Ex
Undefined instruction Arithmetic overflow
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Exceptions are unexpected or error events. Ex
Undefined instruction Arithmetic
overflow EPC Exception Program Counter A 32
bit register to hold the address of the affected
instruction
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Exceptions are unexpected or error events. Ex
Undefined instruction Arithmetic
overflow EPC Exception Program Counter A 32
bit register to hold the address of the affected
instruction Cause A 32 bit register to record
the cause of the exception.( Option is to vector
into OS) Undefined instruction 0 Arithmetic
overflow 1 OS entry point for exception
handling C0000000 hex
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Undefined instruction Save Address in EPC, Load 0
in Cause, Jump to C0000000
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6
BEQS8 JS9 S
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Undefined instruction Save Address in EPC, Load 0
in Cause, Jump to C0000000
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0)
ALUOut, (LWSW)S2 RS6 BEQS8
JS9 OtherS10 S S10
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Undefined instruction Save Address in EPC, Load 0
in Cause, Jump to C0000000
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0) ALUOut,
(LWSW)S2 RS6 BEQS8
JS9
OtherS10 S S10 PC 4 EPC, 0
Cause,
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Undefined instruction Save Address in EPC, Load 0
in Cause, Jump to C0000000
S0 MPC IR, PC 4 PC, S1
S S1 RIR25-21 A, RIR20-16
B, PC shlt2sign_ext(IR15-0) ALUOut,
(LWSW)S2 RS6 BEQS8
JS9
OtherS10 S S10 PC 4 EPC, 0
Cause, C0000000 PC, S0 S
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• Exam 2 Review
• Twos Complement Arithmetic
• Ripple carry ALU logic and performance
• Look-ahead techniques, performance and equations
• Basic multiplication and division (
  non- restoring) algorithms
• IEEE 754 floating point standard (definition
  provided)
• Write a sequence of register transfers to
  implement a given instruction for MIPS
• Given a set of Register Transfers, design the
  control needed for some component