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Power Reduction Technique

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http://www.amis.com/pdf/process_specifications/c5_ss.pdf. Power versus voltage (N=1) ... The Delay versus Voltage graph can be used for interpolating the ... – PowerPoint PPT presentation

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Title: Power Reduction Technique


1
Power Reduction Technique
  • Parallelism in circuits using duplication of
    logic

2
OUTLINE
  • Problem Definition
  • Steps for Implementation
  • Background Information
  • Experimental Results
  • Theoretical Results
  • Conclusion
  • Lessons

3
Problem Definition
  • Design a 32 bit adder with parallelism
  • Operational speed must be the same (throughput
    constant)
  • Show it to be an effective Power reduction scheme

4
Block diagram Representation
5
Implementation Technique
  • MODELSim, Leonardo, Design Architect, Eldo
  • Technology used ami 0.5
  • Delay calculation( 50 of the rise time)
  • VHDL/Verilog
  • http//www.amis.com/pdf/process_specifications/c5_
    ss.pdf

6
Power versus voltage (N1)
Voltage Dynamic Power (mW) Static Power (uW)
5 22.4128 33.471
4 13.1289 21.020
3 7.9665 11.658
2 3.7048 5.114
1 0.5181 1.256
7
Dynamic Power v/s Voltage (N1)
8
Power versus voltage (N2)
Voltage Dynamic Power (mW) Static Power (uW)
3.5 18.095 56.18
3 12.775 48.11
2.5 9.0875 34.62
2 6.0511 22.01
1.5 2.2306 14.32
9
Dynamic Power v/s Voltage (N2)
10
Delay versus Voltage (N1)
Voltage (Volts) Delay (Nano secs)
5 0.34
4 0.41
3 0.608
2 1.01
1 3.77
11
Delay versus Voltage (N1)
12
Experimental Results
Delay (nS) Voltage (N1) Voltage (N2)
0.34 5 3
0.41 4 2.5
0.608 3 1.5
1.01 2 NA
13
Power Reductions
Reference voltage (V) Power (mW) (N1) Voltage (V) Power (mW) (N2) Reduction
5 22.41 3 12.77 42.99
4 13.12 2.0 6.051 53.39
3 7.995 1.5 2.2306 72.17
14
Theoretical Calculations
  • Power CVDD2
  • The Delay versus Voltage graph can be used for
    interpolating the voltage levels for various
    degrees of parallelism

15
Theoretical v/s Experimental
Voltage (Reference) V Theoretical Value (V) Experimental Value (V) Power Reduction (Theoretical) Power Reduction (Experimental)
5 3.2 3 52.40 42.99
4 2.3 2.5 64.60 53.39
3 1.4 1.5 78.12 72.17
16
Conclusions
  • Parallelism is an effective power reduction
    technique
  • However, it causes extra designing effort
  • The theoretical calculations do not exactly match
    because the overhead hasnt been taken into
    account in it

17
Lessons
  • Patience!!!!!!!!!!!!!!!!!!!!!!!!!

18
References
  • Dr Agrawals website
  • Mentor manuals

19
  • Thank You!!!!!
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