SC ILP=RC

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SCILPRC

• Chris Gniady, Babak Falsafi, and T. N. Vijaykumar

February 24th 2006
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• SC execute memory operations one at a time, in
  program order
• RC no order unless explicitly requested by
  software (programmer)
• ILP out of order and speculative execution

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• SC - runs like RC, talks like SC
• Speculates on all instructions, including stores
  RC-like freedom
• Detects when SC is violated and recovers
• L2 cache must cooperate (memory and remote nodes
  expect SC)

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• Rollback when speculative block is
• Invalidated by DSM directory
• Read by remote node
• Replaced from L2 cache
• Livelock safety
• Instruction that caused rollback executed and
  retired non-speculatively
• Deadlock safety
• No coherence message processing while in rollback
  mode

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• SC adds hardware SHiQ and BLT

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• SC ILP RC if hardware has
• Speculative loads and stores
• Enough space for speculative processor and memory
  state
• No slowdown due to added complexity
• Infrequent rollbacks in execution

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• Rollback frequency depends on SW
• SW can generate high amounts of
• Data races
• False sharing
• Cache conflicts
• Argument such SW is unlikely to benefit from DSM
  anyway

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• Evaluation using simulation
• Scientific code benchmarks
• 8 MIPS R10K cores

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• Questions ?