Dan Bowerman

1
Status of the Calice Electromagnetic Calorimeter
Dan Bowerman Imperial College 27th May 2004
2
Prototype Overview

• 30 layers of variable thickness Tungsten
• Active silicon layers interleved
• Front end chip and readout on PCB board
• Signals sent to DAQ

200mm

• PCB contains VFE electronics
• 14 layers, 2.1mm thick
• Analogue signals sent to DAQ

• Tungsten layers wrapped in Carbon Fibre
• 8.5 mm for PCB Silicon layer

360mm
360mm

• 6x6 1x1cm2 silicon pads
• Connected to PCB with conductive glue

3
Silicon Wafers
Each Wafer Matrix of 6 x 6 pixel of 1 cm2
4 High resistive wafer 5 K? cm Thickness
525 microns ? 3 Tile side 62.0 mm including
Guard ring In Silicon 80 e-h pairs / micron ?
42000 e- /MiP Capacitance 21 pF Leakage
current 5 20 nA Full depletion bias 150
V Nominal operating bias 250 V
Require 270 active wafers for the Prototype
150 to be produced by Institute of Nuclear
Physics Moscow State University First test
production February 2003, 130 wafers produced
already 150 to be produced by Institute of
Physics, Academy of Sciences of Czech
Republic,Prague First test production March
2004, 15 produced already, full production by end
of June
Both sets of Wafers are of high quality
4
Very Front End Electronics
VFE consists of
1 channel

• Preamp with 16 gains (gain selected offline)
• CR-RC shaper (200ns), track and hold
• 18 channels in, one Multiplexed output

OPA
MUX out Gain10
Amp
MUX out Gain1
OPA
Each chip serves 18 channels, 2 chips per
wafer Linearity 0.2 Range 600
MIPS Crosstalk lt 0.2
3 generations of improving production Numbers
quoted refer to V2 V3 produced, and being tested
5
Production Testing

• PCB designed in LAL-Orsay, made in Korea (KNU)
• 60 Required for Prototype, ready in July
• An automatic device is use to deposit the
  conductive glue EPO-TEK EE129-4
• Gluing and placement (? 0.1 mm) of 270 wafers
  with 66 pads, 10 000 points of glue
• About 10 000 points of glue.
• Production line set up at LLR

12 VFE chips
2 calibration switch chips
Line Buffers To DAQ
6 active silicon wafers
6
Production Testing

• Must validate assembly, mounting and performance
  of each PCB
• Dedicated DAQ system to test individual PCBs
• Use in conjunction with Cosmic test bench, or
  90Sr ß decay

Interconexion Panel
Trigger
generator
Scintillator
Plane
VFE-
Daq board and
PCB
control signals
to VFE PCB
Scintillator
Plane
7
First tests with prototype PCB
external signal

Sr90 source ? trigger ? read 6 channels Only
ONE with signal
Noise
MIP

5
Noise
output ADC
8
Prototype DAQ

• Use custom VME readout board
• Based on CMS tracker front-end board (FED)
• Uses several FPGAs for main controls
• Dual 16-bit ADCs (500 kHz) and 16-bit DAC
• On-board buffer memory 8 Mbytes. 1.6k event
  buffer, no data reduction

• Prototype design completed last summer
• Two prototype boards fabricated in November
• Noise 1ADC count
• Linear to 0.01
• Gains uniform to 1

Further tests, final production July
9
Full Chain - Cosmics

• Now attach PCB to Prototype DAQ board Full
  Detector Chain
• Use track interpolation from scintillators to
  select events

• Clear cosmic MIP peak seen, 45 ADC counts above
  pedestal
• MIP 200 keV calibrates ADC so 1 count 4.4
  keV
• 32k full range 700 MIPs requirement gt 600 MIPs
  
• Noise per channel 9 ADC counts 40 keV
• MIPnoise 51 requirement gt 41
• Expect 7.51 from initial tests with new VFE chip

• Selecting events with at least one pad gt 40 ADC
  counts (4s cut)
• Clearly highlights the active 6?6 cm2 silicon
  wafer
• Can survey wafer positions, and cross-check
  readout positions

10
Full Chain - Cosmics
Scintillator
Y-Z plane
X-Z plane
Wafer
Scintillator

• Example of Cosmic Event
• Passes through scintillators
• Extrapolated through silicon
• Appears as clear signal above background

11
Future Technology RD
RD for the full scale detector is also
progressing

• Prototype design is not realistic as
• -Industry cannot build 1.6 m PCB tendancy is for
  smaller PCBs
• High line capacitance ? very noisy
• Large number of lines ?crosstalk issue and many
  PCB layers

Possible solution VFE Chip mounted near wafers

• -1 chip per wafer
• Low power issue
• Cooling issues
• Temperature distribution in module?
• Fake signal due to e.m. showers in chip

Simulation Thermal dissipation with internal
cooling at the border with liquid flow
Two chips produced this year, simulation
underway, cooling prototype and test bench being
developed. Future DAQ ideas also being
investigated
Big Issue Funding mechanism for this RD not
established
12
Prototype Status and Timelines
Prototype components status
All elements of the prototype are at or are close
to schedule All wafers/PCBs tested by October
2004 Plan for low energy electron test beam at
DESY before the end of the year High energy
electron/hadron test beams with HCAL at FNAL/IHEP
next year
13
Conclusions

• Great deal of progress in the past 18 months
• All prototype components in production and at or
  close to schedule
• Performance of individual components at or better
  than required
• Complete detector chain in place and tested
• Captured Cosmics and ß decays
• Good Signal to Noise
• Extensive testing to ensure quality of prototype
  components
• Preparing for Test Beam at DESY by the end of the
  year
• Full ECAL HCAL hadron test beam next year

14
Ecal concept

• Jet Energy resolution is key to LC detector
  performance
• Energy Flow technique gives best Jet Energy
  resolution
• Requires tracking calorimetry to resolve
  individual particles
• Tracking Calorimeter requires high
  granularity/segmentation
• Ecal Si-W sampling calorimeter, 40 layers, 1x1
  cm2 pads, 32 M channels, 24X0 in 20 cm
• Require Testbeam Monte Carlo tuning to
  accurately determine possible jet resolution