1C Capstone Design

1
1/C Capstone Design

• 2009-2010
• Project Ideas from the Faculty

2
IED War Games Challenge

• Faculty Member Ensemble cast (Salem, Firebaugh,
  Mechtel, Ngo, Rakvic, Shey, Jenkins, may be
  others)
• Divided into blue league and red league events
• Blue league events
• Build robot to identify and collect metal objects
• Autonomous or RC operation modes
• Points for handling varying terrain
• Red league events
• Interfere with blue teams
• Hit simulated convoy
• Stationary or robot-mounted
• Builds on metal detector and line-following robot
  labs in EE411
• Brief in Fall by USMC officers with operational
  experience
• Funded by JIEDDO -- True fleet relevance

3
e-Zapper Automation
Deactivation without detonation

• Mentors Prof. Ciezki, Prof. Ziegler (Physics),
  Prof. Nelson (ME), Prof. Tankersley (Physics)

4
e-Zapper Project Goals

• Convert Weapon Firing Specs into a Sequential
  Logic Diagram
• Convert Block Diagram into LabView Program
• Implement a User Interface

5
e-Zapper Interface Issues

• Develop proper Interface between Hardware and
  Computer
• Learn how to Configure and Use National
  Instruments DAQ Modules

6
e-Zapper LabView Design

• Create User Panel
• Implement Protection Scheme

7
Persistent SurveillanceSensors or Network
Operation

• Mentor Prof. Anderson
• Sensor network for persistent surveillance of a
  situation like guarding a convoy route from
  insurgent interference
• Last year developed a basic network of 8 nodes
  and demonstrated simple operation of the network.
• This year
• Interface with one or more physical sensors via
  I/O ports.
• Develop resistance to jamming and
  denial-of-service attacks, as well as smarter
  network operation.

8
Persistent Surveillance Objectives

• Fall 2008
• (a) Design one or more sensors that can interface
  with the PS board.
• Develop an interface protocol (Logic/USB/RS-232)
  that can communicate with the sensors.
• (b) Incorporate embedded Linux on the PS board.
• (b) Control ZigBee parameters through software.
• Spring 2009
• (a) Integrate sensors with the PS board.
• (a) Demonstrate operation of the network with
  sensor-enabled boards. Design one or more
  sensors that can interface with the PS board.
• (b) Demonstrate ability of the system to sense
  and adapt to changing network conditions.
• (b) Demonstrate robustness to threats and loss of
  nodes.

9
Beagleboard SDR Interface Board
Mentor Prof. Anderson Problem The software
radio community is in dire need of a low-cost,
moderately high performance embedded development
platform. Goals Develop an FPGA-based
interface board between the Beagleboard (a 150
high-performance embedded processing platform)
and COTS Analog Front Ends (AFEs).
10
Beagleboard SDR Interface BoardDesign Objectives
Rev. 2 Hardware design completed and interfacing
drivers written by ENS Schaertl in Summer
2009. Basic AM Transmitter demo documented and
released. Want to demonstrate complete system
integration with a version of GNU radio running
on the Beagleboard. Added bonus work with
Cool Canadians and Ex-British.
11
Beagleboard SDR InterfaceGoals
Fall 2009 Demonstrate AM/FM real-time
demodulation using the Beagleboard and samples
saved to a file. Demonstrate AM/FM transmission
and reception of off-air signals using the
Beagleboard and the interface board. Spring
2010 Demonstrate reception and demodulation of
ships AIS signals either from samples saved to a
file or off-air. Demonstrate communication of two
Beagleboard SDRs using AM/FM or other signals.
12
Dynamic Spectrum Access Testbed

• Mentor Prof. Anderson

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DSA Testbed Overview and Objectives
Create a testbed that will allow two DSA radios
to be evaluated in the presence of a
custom-generated wireless spectrum.
Fall 2009 Behavioral modeling of wireless
spectrum based on measured data. Design testbed
and interconnections. Generate signals using GAGE
Arbitrary Waveform Generator. Spring 2009 Create
emulated spectra using GAGE AWG and behavioral
model. Demonstrate operation of the testbed with
two DSA radios.
14
Project Fiber Optic Cellular Repeater
Mentors Prof. Jenkins, Prof. Anderson, LCDR
Flaherty Problem Cellular signals are weak (or
nonexistent) on the lab deck of Rickover. Goal
Develop a repeater to receive cellular signals,
amplify, filter, and rebroadcast them on the
Rickover lab deck.
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Fiber Optic Cellular RepeaterDesign Objectives

• Receive, filter, and digitize cellular signals
  from an antenna mounted outside Rickover Hall.
• Optically modulate these signals and transmit
  them to a single rebroadcast antennas on lab
  deck.
• Repeat the process for the uplink direction.
• Design the system for future expansion (multiple
  rebroadcast antennas).

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Fiber Optic Cellular Repeater Block Diagram
Antenna on Rickover Terrace
Antenna(s) in Rickover Lab Deck
17
Fiber Optic Cellular RepeaterRough Timeline
Fall 2009 6 Weeks Begin integration of RF front
end (including antenna) and FPGA using AY09
design 12 Weeks Verify functionality of RF front
end and FPGA for downlink, define all parts for
optical interface EOS Parts ordered, begin
redesign of FPGA Spring 2010 6 Weeks Complete
FPGA design, integrate with optical interface,
verify operation with real signals 12
Weeks Build remainder of downlink, verify full
downlink functionality, build uplink EOS Demonstr
ate full system operation, project writeup
18
Surveillance System for Face Detection/Recognition

• Mentors Prof. Ives and Prof. Matey
• 2 Mids
• Approach
• Two cameras
• Low resolution webcam
• Surveil scene, detect people
• Detect face, steer high-res camera to capture
  picture of face
• High resolution camera
• Point to, zoom in, capture hi-res picture of face
• Pan-tilt mount
• Move hi-res camera to point to face
• Supporting Software
• A variation of Jeremy Papons Trident project
• abandoned luggage

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Surveillance System
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Surveillance System

• Components Interfaced To A Personal Computer
• Universal Serial Bus (USB) Connection Used for
  Low-Resolution Webcam and High Resolution Still
  Frame Camera
• RS-232 Serial Connection Used for Pan/Tilt Mount
  (?)
• Control of System Through a Graphical User
  Interface (GUI)

21
Surveillance System Tasks

• Determine/acquire suitable pan-tilt mount,
  webcam, high-res camera, other hardware
• Use C/C/C for real-time algorithm development
  (OpenCV library)
• PC interface to cameras
• Person detection/Face detection
• Steer high res camera
• Hi-res camera control (zoom, focus, snap picture)
• Face recognition algorithm
• GUI for user control (start/stop/display image
  and live video)

22
Surveillance System

• Expected results
• Dual-camera acquisition system for future
  experiments
• Various applications target tracking, gun
  direction, etc.
• Report detailing design, construction, operation
  and performance
• Miracles required
• NONE

23
Iris Recognition at a Long Distance

• Mentors Prof. Matey, Prof. Ives
• Currently iris recognition requires up close and
  personal contact goal is to use it from a
  distance.
• Approach
• 2 cameras
• Wide field of view to detect faces and steer
  high-res camera (telescope)
• High res/ narrow field of view (telescope) for
  capturing image
• Software modules for face finding, camera, and
  telescope control.
• Will use existing modules for iris recognition

24
Detection of a Bullet Shock Wave in Helicopter
Noise Mentors Prof. Antal A. Sarkadyand Major
Bryan J. Forney

• Task
• Design a Hardware/Software Box that Suppresses
  the Helicopter Noise and Detects a Ballistic
  Shock Wave
• Use Recorded Bullet Shock Waves from NRL
• Use Recorded Helicopter Noise from USMC
• Applicable Techniques
• High-Pass Filter Design
• Look-Ahead Digital Filter Design

25
Ballistic Shock Waves in AirSummary Report
1Professor M. S. Korman, Physics Dept., U. S.
Naval Academy andProfessor Antal A. Sarkady, ECE
Dept., U. S. Naval AcademyJune 12, 2009

• Fig. 2. Asymptotic shape of the ballistic shock
  wave, N Wave

According to Stoughton (1987), who references
Whitham (1952), the peak pressure amplitude
and period T of the N wave are related to
projectile length L , diameter d, distance from
the trajectory b, and Mach number M.
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Properties of a Ballistic Shock Wave
Fig. 1. The real time ballistic shock wave
determined at miss distances of r 50, 100, 150,
, 500 m. The rise time is t T/5 for each
case.
Fig. 2. The rms spectrum for the ballistic shock
wave determined at miss distances of r 50, 100,
150,., 500 m. The rise time is t T/5 for each
case.
27
Helicopter Noise Levels
28
Helicopter Noise Sources
29
A Wireless Controlled Smart H-Bridge for
RobotsMentors Prof. Antal A. Sarkady
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H-Bridge Design Tip 1

• Use 4 N-Channel HEXFET Power MOSFETs IRFP2907

VDSS 75V RDS(on) 4.5mO ID 209A
TO-247AC
Ciss Input Capacitance 13000 pf _at_ VGS 0V
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H-Bridge Design Tip 2

• Use Optically Isolated High-Side Drivers
• with Totem - Pole Output

Features 0.4 A minimum peak output current
High speed response 0.7 ms maximum propagation
delay over temperature range Ultra high
CMR minimum 10 kV/ms at VCM 1 kV Wide
operating temperature range 40C to 100C
Wide VCC operating range 10 V to 30 V over temp.
range Available in DIP8 and SO8 package
Safety approvals UL approval pending, 2500 Vrms
for 1 minute.
32
A Practical 70V, 50A H-Bridge
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The MC68HC908QB8 Micro
Freescale CodeWarrior Development System
In-circuit Programming C Program Development
Assembly Program Development
8k bytes of FLASH, 256 bytes of RAM, 10 channel
ADC 10/8 bit, 4 PWM
34
Xecom XE900SL10
Features Serial Control and Configuration of
the Wireless Link. Supports 65,000 unique node
addresses Output Power Programmable from 0 to
10 mW Maximum Receiver Sensitivity -100 dBm
Obstructed signal range to 300 feet Wireless
Data Rate 76.8K bps, half-duplex typical
throughput, 12K bps Power Consumption 55 mA _at_
3.3 Volts when transmitting at 10 mW less
than 1 mA in Sleep Mode or Power-Down modes
35

Class D Audio Amplifier Design

• Mentor Prof. Salem

http//www.irf.com/technical-info/appnotes//an-107
1.pdf
36
Class D Audio Amplifier Design

• Background research
• Why use a Class D approach
• What other amplifiers exist
• Design and build an audio amp to meet minimum
  specifications
• gt 100 W into 8 O speaker
• lt 0.1 THD over audio range at 100 W
• Single RCA jack input and wire terminal output
• Final packaged unit occupies lt 2000 cc
• Operate at max output indefinitely in a 25 ºC
  ambient
• Final project must be documented to meet/exceed
  specifications

37
Microstrip Antenna

• Mentor Prof. Mechtel
• Must have taken EE372 in 2/C year

38
Microstrip Antenna Deliverables

• End of Semester
• Substrate materials chosen, ordered and
  delivered.
• Patch antenna design.
• Patch antenna Sonnet simulation.
• Antenna performance test plan.
• Fixtures for antenna testing fabricated/delivered.
  
• End of Year
• Antenna test results.
• Antenna test results analysis.
• Redesign of patch antenna based on test results.
• Simulation, fabrication and test of redesign.
• Antenna test results and analysis of redesigned
  antenna.

39
Implementation of aSuperscalar CPU

• Mentor CAPT Cameron
• Objective
• Produce a dual-pipelined CPU
• Implement a standard instruction set
• Support interrupts
• Demonstrate the proper functioning of the CPU
• Deliverables
• December
• Specify instructions to be implemented
• Show an overview of the implementation design
• Include a schedule for completion
• April
• Explain the design
• Explain the test program
• Interpret the results

40
The Futuristic Computer

• Mentors Prof. Rakvic, CAPT Walker
• What
• Prototype a futuristic computer with the Beast
  of Burden
• Quad Core Xeon Processor
• 2 Stratix III FPGAs (high-end)
• Why
• FPGAs are growing in popularity
• Soon they may be in your computer..

System Memory
Motherboard



Quad Core Xeon CPU
FPGA
Quad Core Xeon CPU
Intel Northbridge Chipset
FPGA
41
The Futuristic Computer Tasks

• 1. Implement Application on Quad-core PC without
  FPGAs
• Simple application in C code on Linux
• Multi-thread
• Develop understanding of application
• 2 Implement portion of application on FPGAs
• Find parallelism
• Port to FPGA module
• 3 Combination
• Use VHDL and C
• reference design to
• learn Direct Memory
• Addressing process
• Drivers provided

System Memory
C application
VHDL



FPGA
Quad Core Xeon CPU
Intel Northbridge Chipset
FPGA
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The Futuristic Computer Tasks, cont.

• 4 Performance Analysis
• Bottleneck identification
• Memory latency?
• Future predictions
• Utilizing scaling trends
• Beast of Burden also makes statements from the
  future

// Michigans current ranking 91 if
(UM.2010.ranking gt 91) delete UM Else if
(UM.2010.ranking lt 2) cout ltlt UM is Number 1
again
UM is Number 1 again
43
3D Integrated Circuits for Trust

• Mentors Prof. Rakvic and CAPT Rudd
• Enemies can add transistors to dies (manufactured
  abroad)
• Lets make it harder to reverse engineer the dies
• Use 3D integrated circuit technology for trust

• Randomly place transistors across the 3D dies
• Transistor A may not be right next to transistor
  B now
• Die to die VIAs will be made by us
• Manufacturers will have a tougher time figuring
  circuit out

44
3D Integrated Circuits for Trust

• Student task analyze performance impact of
  randomized 3D circuit
• Take an original VHDL design and find critical
  paths
• Use netlist and simulator
• Add 3D randomness
• With a high level language
• Recalculate paths with Manhattan distance
  estimator
• Adjust netlist to incorporate new delays
• Use new netlist with simulator to find new
  critical paths
• Learning Objectives HDL, HLL, Low level design,
  timing

45
Sea Surface Acoustic Monitor

• Mentors Prof. Firebaugh, LT Janssen
• Need The Woods Hole Oceanographic Institute is
  developing a buoy-mounted system for
  climate-change studies. The system requires a
  better understanding of the acoustic environment
  of a buoy. A sensor is needed that can monitor
  and record the acoustic spectrum on the surface
  side of a small buoy over the course of weeks to
  months while not being affected by the harsh
  environment near the sea surface .

46
Sea Surface Acoustic Monitor

• Block diagram

Solar panel
Solar controller
Battery
Mic
Data Storage
Microcontroller
User Settings
Display (debug tool)
Weather-protected chassis
47
FPGA Based Real-time Video Enhancement

• Mentor Prof. Ngo

48
FPGA Based Real-time Video Enhancement
Original Images
Enhanced Images
49
FPGA Based Real-time Video Enhancement Block
Diagram
Cyclone II FPGA
Video Decoder
Enhancement Module
Interface unit
Interface unit
Video Encoder
Video in
VGA
Altera DE2 Board
Enhancement methods Histogram
equalization, Retinex algorithm Other
algorithms
50
FPGA Based Real-time Video Enhancement Tasks

• Understand an image enhancement algorithm
• Develop a software program in high level language
  (C/C, Matlab, etc) to simulate the algorithm
• Design and implement the enhancement algorithm
  using VHDL
• Demonstrate a prototype system on the Alteras
  DE2 board.

51
Debris Resistive/Acoustic Grid Orbital Navy
Sensor (DRAGONS)

• Mentors Prof. Anderson and Prof. Ngo
• Design and build a system to detect and measure
  time, size and vibration data resulting from a
  hypervelocity particle impact on a payload
• DRAGONS system is comprised of an acoustic
  subsystem (ACS) and a resistive grid subsystem
  (RGS) monitored and controlled by a control and
  data storage subsystem (CDSS) that shall detect a
  hypervelocity particle impact in low-earth orbit
  and collect impact data. The purpose of the
  resistive grid subsystem is to verify and
  validate information from the acoustic subsystem

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DRAGONS Block Diagram
53
DRAGONS Tasks

• A team of 2 midshipmen
• Design and implement a glue-logic unit in an FPGA
  to control data flow in the ACS and RGS
  subsystems.
• Design and implement the controlling logic in the
  8051 processors to interface with the FPGAs. The
  main responsibility of the 8051 is to read and
  store data in the memory when an event is
  detected.

54
DRAGONS Proof of Concept
55
Guitar Hero Playing Robot

• Mentors LT Shey and Prof. Ngo
• Play Single Player Guitar Hero with gt 95
  accuracy
• Entire system should be compact and easily
  mountable on the controller. Professional
  looking
• Powered off conventional 120V 60Hz Source
• Rock out

56
Guitar Hero Playing Robot Block Diagram
Project Boundary
Power Circuit
Mid Hard
Mid Rocker
FPGA DE2 Board
Actuators/Solenoids
Digital Signal
Physical Signal
Analog Signal
TV
PS2
Guitar Hero Controller
PS2
57
Guitar Hero Playing Robot Tasks

• Team Member 1
• Design all hardware for the system, to include
  power supplies, solenoids and actuators.
• Design brackets to mount the hardware to the
  controller
• All final deliverables will be PCBs with enclosed
  in cases
• Team Member 2
• Implement FPGA Program to detect when desired
  notes need to be played by decoding video and
  output digital values for what keys are being
  pressed.

58
ATV Competition

• Mentors LT McMunn, Prof. Caton (ME), Prof. Ciezki

59
Solar Splash Competition

• Mentors CDR Marks, LT Lust (ME), Dr. Ciezki
• Collegiate competition for solar powered boats
• Joint project with ME (1/C Islin, LeMaster and
  Odenwald)

60
Solar Splash Competition

• Event details
• Date June 9 13, 2010
• Location Fayetteville, AR
• Competiton
• Slalom
• Endurance
• Sprint
• Website www.solarsplash.com
• On the web
• Slalom http//www.youtube.com/watch?vW7-svctmQ_o
  
• Sprint http//www.youtube.com/watch?vtDqowjnZYoA

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Related to Solar Splash

• Maximum Power Point Tracker Vary Converter Set
  Point to Maximize Panel Output Power as Sun
  Intensity Changes

62
Microrobots

• Mentors Prof. Firebaugh and Prof. Piepmeier
  (WSE)
• Focuses on the creation and control of micro- to
  milli-scale robots that perform soccer-related
  agility drills for the RoboCup Nanogram League.
  Such microrobots might ultimately be used for
  minimally-invasive surgery, microassembly of
  engineered materials, or intelligence gathering.
• Two project areas
• Magnetic Microrobot.
• Soccer-Playing Bristle-Bot.

63
Microrobots (Magnetic)

• The foundation
• Magnetic microrobot under production
• Load module for controlling large currents in
  coils
• A selection of electromagnets, all currently too
  small for the application
• The task
• Design and construction of electromagnet cage
• Construction of LabVIEW interface for control
• Development of algorithm for controlling motion
• Machine vision integration for autonomous control

64
Microrobots (Bristlebot Soccer)

• The foundation
• Summer intern work with differential drive
  microrobots and scavenged RC car interfaces
• The task
• Optimize bristlebot design
• Adapt RC system for computer control
• Machine vision integration for autonomous control.

65
Parkinson Satellite Communication Network and
Spacecraft Bus Platform

• Mentor Rakvic, joint with Aero
• Be part of team that develops a satellite that
  will launch into orbit
• Goals
• Reliable technology for communications network
• Significant available space for ride-share
  payloads
• Acts as foundation design for spacecraft bus

66
PSAT Concept

• A Low Cost, Global Satellite Data Relay System
• Small, Low Power, Low Cost Ground Terminals
• Low Cost, Standardized Satellite Payloads
• Tasking and Data Dissemination Over The Internet
• ODTML System Consists of
• 1) RF Terminals, GSCTs
• 2) ODTML Satellite Payload (SCP)
• 3) Ground Station Connected to Internet
• Relays Messages From Buoys (and Other Remote
  Sensors) to Users on the Internet

• ODTML PAYLOAD
• Multiple UHF Frequencies
• FPGA Controller

GROUND STATION
Ocean Buoys w/ RF Terminals
INTERNET

• Ground Segment
• In-Theater Downlink to Portable Ground Station
  With Gateway to Internet

67
PSAT System Operation

• Primary Control Station at USNA
• Backup Control Stations in
• -Oregon
• -Hawaii
• -Japan
• -New Zealand
• -Australia
• -Canary Islands
• Dozens of Capture Stations
• Internet Linked

68
PSAT Executive Summary

• Sun pointing ACS
• CubeSat
• 3,405 cm3 and 4.5 kg
• PSat - 2.183 kg each
• Payload Power available
• 2 Watts (relegated)
• Does not include design margin
• Payload Mass/Vol available
• M .5 kg (relegated)
• V (3.4 in)3