Von Neumann Model

1
Von Neumann Model

• Chapter 4

2
Outline

• Basic Components
• Memory, Processing Unit, Input Output, Control
  Unit
• LC-3 An Example von Neumann Machine
• Instruction Processing
• The Instruction, The Instruction Cycle
• Fetch, Decode, Evaluate Address, Fetch Operands,
  Execute, Store Result
• Changing the Sequence of Execution
• Stopping the Computer

3
Harvard Mark I
4
John von Neumann EDVAC
5
Memory

• What is stored in memory?
• How many memories do we need?

6
What is an instruction?
7
von Neumann Model
8
von Neumann Model
9
Memory
ADDR
DATA IN
OUT
IN
MAR
MDR
IN
OUT
DATA OUT
WE
10
von Neumann Model
CONTROL
CONTROL
INPUT
OUTPUT
MDR
MAR
11
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
Control
PC
LD.PC
1
PCMUX
LD.REG
2
3
3
16
SR1
SR2
16
16
16
FINITE STATE MACHINE
SR2MUX
Processor
A
B
2
R
IR
LD.IR
gateALU
16
GateMDR
16
16
MDR
MAR
MEMORY
LD.MDR
LD.MAR
MEM.EN, R.W
12
Issues

• Memory
• MAR, MDR
• Processing Unit
• Register File, ALU (size)
• Input and Output
• KBDR, KBSR, DDR, DSR
• Control
• FSM, PC (Instruction Pointer), IR

13
The central idea in the von Neumann model of
computer processing is that the program and data
are both stored as sequences of bits in the
computer's memory, and the program is executed,
one instruction at a time, under the direction of
the control unit.
14
Instructions
ADD
15
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
Control
PC
LD.PC
1
PCMUX
LD.REG
FETCH
2
3
3
16
SR1
SR2
16
16
16
FINITE STATE MACHINE
SR2MUX
Processor
A
B
2
R
IR
LD.IR
gateALU
16
GateMDR
16
16
MDR
MAR
MEMORY
LD.MDR
LD.MAR
MEM.EN, R.W
16
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
Control
PC
LD.PC
1
PCMUX
LD.REG
2
DECODE
3
3
16
SR1
SR2
16
16
16
FINITE STATE MACHINE
SR2MUX
Processor
A
B
2
R
IR
LD.IR
gateALU
16
GateMDR
16
16
MDR
MAR
MEMORY
LD.MDR
LD.MAR
MEM.EN, R.W
17
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
Control
PC
LD.PC
1
PCMUX
LD.REG
2
3
3
16
SR1
SR2
EVALUATE ADDRESS
16
16
16
FINITE STATE MACHINE
SR2MUX
Processor
A
B
2
R
IR
LD.IR
gateALU
16
GateMDR
16
16
MDR
MAR
MEMORY
LD.MDR
LD.MAR
MEM.EN, R.W
18
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
Control
PC
LD.PC
1
PCMUX
LD.REG
2
3
3
16
SR1
SR2
FETCH OPERANDS
16
16
16
FINITE STATE MACHINE
SR2MUX
Processor
A
B
2
R
IR
LD.IR
gateALU
16
GateMDR
16
16
MDR
MAR
MEMORY
LD.MDR
LD.MAR
MEM.EN, R.W
19
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
Control
PC
LD.PC
1
PCMUX
LD.REG
2
EXECUTE
3
3
16
SR1
SR2
16
16
16
FINITE STATE MACHINE
SR2MUX
Processor
A
B
2
R
IR
LD.IR
gateALU
16
GateMDR
16
16
MDR
MAR
MEMORY
LD.MDR
LD.MAR
MEM.EN, R.W
20
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
Control
PC
LD.PC
1
PCMUX
LD.REG
2
3
3
16
SR1
SR2
STORE RESULT
16
16
16
FINITE STATE MACHINE
SR2MUX
Processor
A
B
2
R
IR
LD.IR
gateALU
16
GateMDR
16
16
MDR
MAR
MEMORY
LD.MDR
LD.MAR
MEM.EN, R.W
21
Instructions
LDR
22
Flow Control

• Normally we execute instructions one after
  another
• When might we not want to do this?

23
Instructions
JMP
24
Stopping
Clock
S R
25
gateMARMUX
gatePC
3
REG FILE SR2 SR1 OUT OUT
DR
PC
MARMUX
LD.PC
1
16
PCMUX
LD.REG
2
3
3
16
SR1
SR2
ZEXT
ADDR2MUX
70
2
ADDR1MUX
16
16
16
16
SEXT
100
0
16
SEXT
40
SEXT
80
FINITE STATE MACHINE
SR2MUX
SEXT
50
LD.CC
A
B
2
R
IR
LD.IR
LOGIC
gateALU
16
16
GateMDR
16
16
MDR
MAR
MEMORY
INPUT
OUTPUT
LD.MDR
LD.MAR
MEM.EN, R.W
26
Questions
27
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