Title: JaegerBlalock
1Chapter 6Introduction to Digital Electronics
- Microelectronic Circuit Design
- Richard C. JaegerTravis N. Blalock
2Chapter Goals
- Introduce binary digital logic concepts
- Explore the voltage transfer characteristics of
ideal and nonideal inverters - Define logic levels and logic states of logic
gates - Introduce the concept of noise margin
- Present measures of dynamic performance of logic
devices - Review of Boolean algebra
- Investigate simple transistor, diode, and
diode-transistor implementations of the inverter
and other logic circuits - Explore basic design techniques of logic circuits
3Brief History of Digital Electronics
- Digital electronics can be found in many
applications in the form of microprocessors,
microcontrollers, PCs, DSPs, and an uncountable
number of other systems. - The design of digital circuits has progressed
from resistor-transistor logic (RTL) and
diode-transistor logic (DTL) to
transistor-transistor logic (TTL) and
emitter-coupled logic (ECL) to complementary MOS
(CMOS) - The density and number of transistors in
microprocessors has increased from 2300 in the
1971 4-bit 4004 microprocessor to 25 million in
the more recent IA-64 chip and it is projected to
reach over one billion transistors by 2010
4Ideal Logic Gates
- Binary logic gates are the most common style of
digital logic - The output will consist of either a 0 (low) or a
1 (high) - The most basic digital building block is the
inverter
5The Ideal Inverter
- The ideal inverter has the following voltage
transfer characteristic (VTC) and is described by
the following symbol
V and V- are the supply rails, and VH and VL
describe the high and low logic levels at the
output
6Logic Level Definitions
- An inverter operating with power supplies at V
and 0 V can be implemented using a switch with a
resistive load
7Logic Voltage Level Definitions
- VL The nominal voltage corresponding to a
low-logic - state at the input of a logic gate
for vi VH - VH The nominal voltage corresponding to a
high-logic - state at the output of a logic gate
for vi VL - VIL The maximum input voltage that will be
recognized - as a low input logic level
- VIH The maximum input voltage that will be
recognized - as a high input logic level
- VOH The output voltage corresponding to an
input - voltage of VIL
- VOL The output voltage corresponding to an
input - voltage of VIH
8Logic Voltage Level Definitions (cont.)
Note that for the VTC of the nonideal inverter,
there is now an undefined logic state
9Noise Margins
- Noise margins represent safety margins that
prevent the circuit from producing erroneous
outputs in the presence of noisy inputs - Noise margins are defined for low and high input
levels using the following equations -
- NML VIL VOL
- NMH VOH VIH
10Noise Margins (cont.)
- Graphical representation of where noise margins
are defined
11Logic Gate Design Goals
- An ideal logic gate is highly nonlinear that
attempts to quantize the input signal to two
discrete states, but in an actual gate, the
designer should attempt to minimize the undefined
input region while maximizing noise margins - The input should produce a well-defined output,
and changes at the output should have no effect
on the input - Voltage levels of the output of one gate should
be compatible with the input levels of a
proceeding gate - The gate should have sufficient fan-out and
fan-in capabilities - The gate should consume minimal power (and area
for ICs) and still operate under the design
specifications
12Dynamic Response of Logic Gates
- An important figure of merit to describe logic
gates is their response in the time domain - The rise and fall times, tf and tr, are measured
at the 10 and 90 points on the transitions
between the two states as shown by the following
expressions - V10 VL 0.1?V
- V90 VL 0.9?V VH 0.1?V
13Propagation Delay
- Propagation delay describes the amount of time
between a change at the 50 point input to cause
a change at the 50 point of the output described
by the following - The high-to-low prop delay, tPHL, and the
low-to-high prop delay, tPLH, are usually not
equal, but can be described as an average value
14Dynamic Response of Logic Gates
15Power Delay Product
- The power-delay product (PDP) is use as a metric
to describe the amount of energy required to
perform a basic logic operation and is given by
the following equation when P is the average
power dissipated be the logic gate
16Review of Boolean Algebra
NOT Truth Table
OR Truth Table
AND Truth Table
NOR Truth Table
NAND Truth Table
17Logic Gate Symbols and Boolean Expressions
18Diode Logic
- Diodes can with resistive loads to implement
simple logic gates
Diode OR gate
Diode AND gate
19Diode Transistor Logic
- Since diode gates are limited to AND and OR
functions, the diodes can be combined with
transistors to complete the basic logic functions
such as the following NAND gate
20NMOS Logic Design
- MOS transistors (both PMOS and NMOS) can be
combined with resistive loads to create single
channel logic gates - The circuit designer is limited to altering
circuit topology and width-to-length, or W/L,
ratio since the other factors are dependent upon
processing parameters
21NMOS Inverter with a Resistive Load
- The resistor R is used to pull the output high
- MS is the switching transistor
- The size of R and the W/L ratio of MS are the
design factors that need to be chosen
22Load Line Visualization
- The following illustrates the operation of the
NMOS output (vDS) characteristics where the
following equation describes the load line
23NMOS with Resistive Load Design Example
- Design a NMOS resistive load inverter for
- VDD 3.3 V
- P 0.1 mW when VL 0.2 V
- Kn 60 µA/V2
- VTN 0.75 V
- Find the value of the load resistor R and the W/L
ratio of the switching transistor MS
24Example continued
- First the value of the current through the
resistor must be determined by using the
following - The value of the resistor can now be found by the
following which assumes that the transistor is on
or the output is low
25Example Continued
- For vI VL 0.2V, the transistors vGS will be
less than the threshold voltage, therefore it
will be operating in the triode region. Using the
linear equation for a MOSFET, the W/L ratio can
be found
26On-Resistance of MS
- The NMOS resistive load inverter can be thought
of as a resistive divider when the output is low,
described by the following expression
27On-Resistance of MS (cont.)
When the NMOS resistive load inverters output is
low, the On-Resistance of the NMOS can be
calculated with the following expression
Note that Ron should be kept small compared to R
to ensure that VL remains low, and also that its
value is nonlinear which has a dependence on vDS
28Noise Margin Analysis
- The following equations can be used to determine
the various parameters needed to determine the
noise margin of NMOS resistive load inverters
29Load Resistor Problems
- For completely integrated circuits, R must be
implemented on chip using the shown structure - Using the given equation, it can be seen that
resistors take up a large area of silicon as in
an example 95kO resistor
30Using Transistors in Place of a Resistor
- NMOS load w/ a) gate connected
- to the source b) gate connected
- to ground
- c) gate connected
- to VDD
- d) gate biased to
- linear region
- e) a depletion
- mode NMOS
- Note that a) and b) are not useful
31Static Design of the NMOS Saturated Load Inverter
- Schematic for a NMOS
- saturated load inverter
Cross-section for a NMOS saturated load inverter
32NMOS Saturated Load Inverter Design Strategy
- Given VDD, VL, and the power level, find IDD from
VDD and power - Assume MS off, and find high output voltage level
VH - Use the value of VH for the gate voltage of MS
and calculate (W/L)S of the switching transistor
based on the design values of IDD and VL - Find (W/L)L (load transistor) based on IDD and VL
- Check the operating region assumptions of MS and
ML for vo VL - Verify design with a SPICE simulations
33NMOS Saturated Load Inverter Design Example
- Design an saturated load inverter given the
following specifications
34NMOS Saturated Load Inverter Design Example
35NMOS Saturated Load Inverter Design Example
- For vo VL,MS is off (triode region) and ML is
in saturation, find the W/L ratios of the two
transistors
36NMOS Saturated Load Inverter Design Noise Margin
Analysis
- The basic noise margin equations are still the
same as for previous inverters, but there are
different expressions for the components
The equations can be written as a quadratic
equation,but an iterative process must be used to
solve for VOL and VTNL 1) Choose an initial
VOL 2) Calculate the corresponding VTNL 3) Update
VOL 4) Repeat 2 and 3 until the system converges
37NMOS Inverter with a Linear Load Device
- This alternative inverter has a load transistor
that is biased with VGG defined by the following - This causes the load transistor to operate in the
linear region
38NMOS Inverter with a Depletion-mode Load
- With the addition of a depletion-mode NMOS (VTH lt
0V), it is possible to configure an inverter as
shown - VGSL 0 V for this configuration meaning that ML
is always operating in saturation
39Design of a NMOS Inverter with a Depletion-mode
Load
- To find (W/L)L given iDL
- To find (W/L)S where VH VDD use the same
technique as used for the resistor load inverter
40Noise Margins of a NMOS Inverter with a
Depletion-mode Load
The first two equations assume the MS is
saturated and ML is in triode
The last two equations assume the MS and ML are
in triode
41NMOS Inverter Summary
- Resistive load inverter takes up too much area
for and IC design - The saturated load configuration is the simplest
design, but VH never reaches VDD and has a slow
switching speed - The linear load inverter fixes the speed and
logic level issues, but it requires an additional
power supply for the load gate - The depletion-mode NMOS load requires the most
processing steps, but needs the smallest area to
achieve the highest speed, VH VDD, and best
combination of noise margins
42Typical Inverter Characteristic
43NOR Gates
- Simplified switch model for
- the NOR gate with A on
Two-input NOR gate
44NAND Gates
Two-input NAND gate (left)
- Simplified switch model
- for the NOR gate with A
- and B on (right)
45NAND Gate Device Size Selection
- The NAND switching transistors can be sized based
on the depletion-mode load inverter - To keep the low voltage level to be comparable to
the inverter, the desired RON of MA and MB must
be 0.5RON of MS,Inverter - This can be accomplished by approximately
doubling the (W/L)A and (W/L)B - The sizes can also be chosen by using the design
value of VL and using the following equation
46NAND Gate Device Size Selection (continued)
- Two sources of error that arise are the facts
that VSB and VGS of the two transistors do not
equal. These factors should be considered for
proper gate design - The technique used to calculate the size of the
load transistor for the depletion-mode load
inverter is the exact same as for this NAND gate
47Layout of the NMOS Depletion-Mode NOR and NAND
Gates
48Complex NMOS Logic Design
- An advantage of NMOS technology is that it is
simple to design - complex logic functions based on the NOR and NAND
gates
The circuit in the figure has the logic
function Y A BC BD
49Complex Logic Gate Transistor Sizing
- There are two ways to find the W/L ratios of the
switching transistors - Using the worst case (longest) path and choosing
the W/L ratio such that the RON of the multiple
legs match similar to the technique used to find
the W/L ratios in the NAND Gate - Partitioning the circuit into series
sub-networks, and make the equivalent
on-resistances equal
50Complex Logic Gate Transistor Sizing
- The figure on the left
- shows the worst case
- technique to find the
- sizes where
- (W/L)S2.06 is the
- reference inverter ratio
- for this technology and
- the longest path is 3
- transistors are in series
- The figure on the right
- shows the partitioning
- technique to find the
- sizes which gives two
- 4.12/1 ratios in series
- which is 2(2.06/1)
51Static Power Dissipation
- Static Power Dissipation is the average power
dissipation of a logic gate when the output is in
both the high and low states - IDDH current in the circuit for vO VH
- IDDL current in the circuit for vO VL
- Since IDDH 0 A for vO VH
52Dynamic Power Dissipation
- Dynamic Power Dissipation is the power dissipated
during the process of charging and discharging
the load capacitance connected to the logic gate
Discharging
Charging
53Dynamic Power Dissipation
- Based on the energy equation, the energy
delivered to the capacitor can be found by - The energy stored by the capacitor is
- The energy lost in the resistive elements is
given by
54Dynamic Power Dissipation
- The total energy lost in the first charging and
discharging of the capacitor through resistive
elements is given by - Thus it can be seen that for every cycle
(frequency) that the gate is changed, the dynamic
power dissipation is given by
55Power Scaling in MOS Logic
- By reducing the W/L of the load and switching
transistors of an inverter, it is possible to
reduce the power dissipation by the same factor
without sacrificing VH and VL. This same concept
works for increasing the power which will
increase the dynamic response.
56Power Scaling in MOS Logic
- Original Saturated Load Inverter
- Saturated Load inverter designed to operate at
1/3 the power - Original Depletion-Mode Inverter
- Depletion-mode inverter designed to operate at
twice the power
57Dynamic BehaviorCapacitance in MOS Logic Circuits
- The MOS device has the capacitances CSB, CGS,
CDB, and CGD that need to be considered for
dynamic response analysis, but depending on the
configuration, some of them will be shorted out
as seen in the first figure - The capacitance seen at a node can be lumped
together as seen in the second figure
58Fan-out Limitations
- Static design constraints are not usually
important for MOS logic circuits since they
normally drive capacitive loads (i.e. the gate of
a MOS) - As the number of gates the output (fan-out) of a
logic device has to drive, the load capacitance
increases, and the time response decreases - This notion implies that the fan-out that a logic
circuit can drive will be limited to time delay
tolerances of the circuit
59Dynamic Response of the NMOS Inverter with a
Resistive Load
- The rise and fall times and propagation delays
are given by the relationships - where R and C are the resistance and capacitance
- seen at the output
60Dynamic Response of the NMOS Inverter with a
Resistive Load
- There are four important times that need to be
considered when characterizing the dynamic
response of a logic circuit which are denote t1
t4 in the figure
61Dynamic Response of the NMOS Inverter with a
Resistive Load
- It is also possible to calculate tPHL and tf by a
piecewise analysis technique, and are given by
the following equations
62NMOS Inverter with a Depletion-Mode Load Dynamic
Response
- Just as in the resistive load inverter, the
depletion-mode load inverter has the same dynamic
response characteristics that need to be
considered, and has four times that needed for
calculations
63NMOS Inverter with a Depletion-Mode Load Dynamic
Response
- The following are the basic equations for
calculating dynamic response characteristics
64NMOS Inverter with a Depletion-Mode Load Dynamic
Response Example
- Find tf, tr, tPHL, tPLH and tp for a
depletion-mode load inverter where - (W/L)S 2.06/1 and (W/L)L 1/2.15
- CLOAD 0.1 pF
- VTNS 1 V and VTNL -3 V
- VDD 5 V and VL 0.25 V
- KS (2.06)(25 10-6 A/V2)
- KL (25 10-6 A/V2)/2.15
- Neglect body effect
65NMOS Inverter with a Depletion-Mode Load Dynamic
Response Example
- First find the on-resistances of the two NMOS
66NMOS Inverter with a Depletion-Mode Load Dynamic
Response Example
- It is now possible to calculate the propagation
delays
67NMOS Inverter with a Depletion-Mode Load Dynamic
Response Example
The rise and fall times can be calculated in the
following manner
68NMOS Inverter with a Saturated Load Dynamic
Response
- The following are the basic equations for
calculating dynamic response characteristics and
can be used in a similar manner as the previous
example
69Comparison of Load Devices
- The current has been normalized to 50 µA for
voVOL0.25 V is the figure for the various types
of inverters
70Comparison of Load Devices
- Body effect degrades the performance of the load
device - The saturated load devices have the poorest tPLH
since they have the lowest load current delivery - The saturated load devices also reach zero
current before the output reaches 5 V - The linear load device is faster than the
saturated load device, but still slower than the
resistive load inverter. - The fastest tPLH is from the depletion-mode
device
71Comparison of Load Devices
Simulated fall times for a 0.1 pF load
Simulated rise times for a 0.1 pF load
72Propagation Delay Design Example
- Design depletion-mode load inverter with a
propagation delay (tP) of 2 ns, and find (W/L)S,
(W/L)L tf, and tr such that - CLOAD 10 pF
- VTNS 1 V and VTNL -3 V
- VDD 5 V, VH 5 V and VL 0.25 V
- Base on a reference inverter with
- (W/L)S 2.06/1
- (W/L)L 1/2.15
- Use equations from Table 6.14
73Propagation Delay Design Example
74Propagation Delay Design Example
75Propagation Delay Design Example
- Repeat the example, but use Table 6.16 to include
body effect - First a scaling factor is needed to match this
design problems specifications
76Propagation Delay Design Example
77PMOS Logic
- PMOS logic circuits predated NMOS logic circuit,
but were replaced since they are usually operate
at slower speeds (note the change in the power
supplies)
Resistive Load
Saturated Load
Linear Load
Depletion-mode Load
78PMOS NAND and NOR Gates
NOR Gate
NAND Gate
79Silicon Art
- In the earlier days of IC design, chip designers
were allowed to artistically express themselves
on the wafer by creating images with various
processing steps - However, todays modern foundries have stopped
this since the graphics did not pass the design
rules and were causing fabrication problems
80Silicon Art Examples
81