Radek Dobi Hana Kubtov

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Department of Computer Science and
Engineering, FEE, CTU in Prague
FPGA Based Designof the Railway's Interlocking
Equipments

• Radek DobiáHana Kubátová

DSD 2004 Rennes

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Department of Computer Science and
Engineering, FEE, CTU in Prague
Outline

• Introduction - why safe FPGA applications?
• Basic ideas
• general sheme for fail-safe system
• Dual TMR system with duplicate logic in each node
• System architecture
• Reliability modells
• TMR model
• Dual TMR model
• Conclusions

DSD 2004 Rennes

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Department of Computer Science and
Engineering, FEE, CTU in Prague
Introduction - why safe FPGA applications?

• The function of FPGA block is programmable
• gt The checkers for continuous (on-line) testing
  and a guard block could be integrated inside the
  block
• gt Reprogram in fail case
• Parallel processing
• gt short reaction time in real-time systems
• Utilization of VHDL language
• gt Easy to simulate and verify

DSD 2004 Rennes

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Department of Computer Science and
Engineering, FEE, CTU in Prague
General scheme for fail-safe system

• The guard block
• validates input, output and partial results
• issues a valid/error flag
• can be implemented as a copy of the function comp.

DSD 2004 Rennes

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Department of Computer Science and
Engineering, FEE, CTU in Prague
Dual TMR system with duplicate logic in each node

• redundancy provides fault-tolerant capability

DSD 2004 Rennes

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Department of Computer Science and
Engineering, FEE, CTU in Prague
The fault and error detection

• Error detection
• Non-concurrent on-line testing

DSD 2004 Rennes

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Department of Computer Science and
Engineering, FEE, CTU in Prague
System architecture
DSD 2004 Rennes

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Department of Computer Science and
Engineering, FEE, CTU in Prague
Markov model for TMR system
0 node without fault X node with fault
DSD 2004 Rennes

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Department of Computer Science and
Engineering, FEE, CTU in Prague
Markov model for Dual TMR system
0 node without fault A,B part of node with
fault X both parts of node with fault
DSD 2004 Rennes

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Department of Computer Science and
Engineering, FEE, CTU in Prague
Conclusions

• It is possible to implement fail-safe application
  in FPGA devices
• Reliability model for Dual TMR architecture was
  described and compared with other architectures
• The reliability characteristics show that railway
  interlocking equipment with FPGAs is at least as
  good as other railway interlocking equipment with
  processors or relays
• The first railway application with FPGA is in
  development

DSD 2004 Rennes

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