ECE 426 VLSI System Design

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ECE 426 - VLSI System Design

• Lecture 10 - Communicating ASMs
• March 3, 2003

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Where we are...

• Last Time
• ASM Diagrams
• Discuss Lab 5
• Today - Register Transfer Design
• Handshaking
• FIFOs

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Handshaking

• Basic Idea
• Receiver performs action at request of sender
• Transfer data
• Perform a sub-computation
• Want action to be performed once for each request
• Types of Handshaking
• 1-way
• 2-way
• 3-way
• 4-way (fully interlocked)

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Goals of Handshaking

• Reliably Pass Control Information between ASMs
• Reliably Pass Data Between Interacting ASMs
• ASMs may be driven by different clocks!

S
R
DO_CMD
clk1
clk2
S
R
DATA
clk1
clk2
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1-Way Handshake

• R waits for CMD before starting action
• S asserts CMD to start action

S
R
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1-way Handshake Observations

• Not reliable - why?
• Receiver can miss assertion of CMD if it isnt
  in RWAIT
• Receiver may see assertion of CMD twice if it
  runs on a faster clock than sender

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2-Way Handshake

• 1. Sender asserts CMD and waits for ACK before
  continuing
• 2. Receiver waits for CMD and then asserts ACK

S
R
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2 Way Handshake - Observations

• Reliable if S and R use same clock
• Not reliable if S and R use different clocks
• R could see CMD twice if R faster than S
• S could see ACK twice if S faster than R

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3-Way Handshake

• 1. Sender asserts CMD and waits for ACK before
  continuing
• 2. Receiver waits for CMD and then asserts ACK
• 3. Receiver waits for CMD0 before continuing

SCMD
S
R
CMD
CMD
RW1
ACK
ACK
F
S1
T
ACK
F
CMD
T
RW2
ACK
T
CMD
SN
R1
F
SN-2
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3-Way Handshake - Comments

• Use in some asynchronous bus interfaces
• Not reliable if S is faster than R (see ACK twice)

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4-Way Handshake (Fully Interlocked)

• 1. Sender asserts CMD and waits for ACK before
  continuing
• 2. Receiver waits for CMD and then asserts ACK
• 3. Receiver waits for CMD0 before continuing
• 4. Sender waits for ACK0 before continuing

S
R
RW1
RW2
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4-Way Handshaking

• Works under all circumstances
• Still need synchronizers if clocks are different!

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Handshaking with Multiple Clocks

• CMD, ACK must be synchronized!
• Penalty even more latency!

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Handshaking ASMs with Different Clocks

• Treat signals passing between S and R as
  asynchronous!
• Important never try to handshake on multiple
  bits
• Use synchronizers when crossing clock domains

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Alternative to Handshaking FIFOs

• FIFO First In / First Out Buffer
• S writes data once each clock cycle unless FULL
• R reads data once every clock cycle unless EMPTY

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FIFO Implementation - Software

• Head pointer - marks where to add data
• Tail pointer - marks where to remove data
• Exceptional conditions FULL, EMPTY

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FIFO Implementation - Hardware

• Q How do we calculate FULL EMPTY?

HEAD
TAIL
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FIFO Implementation - Hardware

• Q How do we calculate FULL EMPTY?
• A Must compare head tail pointers

HEAD
TAIL
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FIFO Implementation - Hardware

• Problem
• Read logic (clk1) needs to see Tail pointer
  (clk2)
• Write logic (clk2) needs to see the Head pointer
  (clk1)
• Proposed Solution
• Synchronize Head, Tail
• Problem again! Multiple bits in Head, Tail
• Synchronization wont work on multiple bits!
• Complete Solution
• Use Gray Code for Head, Tail (only 1 bit changes
  at a time!)
• Translate to/from binary internally

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Coming Up

• Timing w/ Design Compiler
• Discuss Project

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Alternative - Buffering with a FIFO

• FIFO First in First Out Buffer

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Synchronization Problems
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Coming Up

• Multiple Controller / Datapath Designs
• Synchronization Issues with Multiple Controllers

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Verification Plan

• Definition A Specification of the Verification
  Effort
• Prerequisite Specification document for design
• Defnining Success - Must Identify
• Features which must be exercisedunder which
  conditions
• Expected Response

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Levels of Verification

• Board
• System / Subsystem
• ASIC / FPGA
• Unit / Subunit

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Levels of Verification

• Connectivity
• Transaction / Cooperative Data Flow
• Functionality
• Ad Hoc
• Designer verifies basic functionality

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Levels of Verification - Notes

• Stable interfaces required at each level of
  granularity

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System Design Issues

• ASM Diagrams
• Synchronization Metastability
• Handshaking
• Working with Multiple Clocks

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