Task II: Physical Design Tools

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Task II Physical Design Tools (Accurate
generation of 3D interconnect structures and
model extraction)

R.W. Dutton
Center for Integrated Systems
Stanford University

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• Outline of Presentation
• Modeling of On-Chip Inductance
• Xiaoning Qi (PhD, now with Sun Microsystems)
• Estimating Bounds on Inductance
• Yi-Chang Lu (PhD candidate, IBM support)
• 3D Geometry Modeling of Interconnects
• Dan Yergeau (Staff member)

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High Frequency Characterization and
Modeling of On-Chip Interconnects

X. Qi, Z. Yu and R.W. Dutton
Center for Integrated Systems
Stanford University
Test devices and measurements per Wong group
Student

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Outline

• Geometry Extraction
• Inductance Extraction
• Field Solver vs. Analytic Formulae
• Experimental Results
• Other Structures and Effects
• Co-planar wave guides
• Substrate Interactions
• Summary

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Approach of This Work

• Automated 3D geometry modeling is based on
  layout and process information (Synopsys
  Arcadia).

• EM field solvers are used to obtain
• golden standard results of inductance
  extraction for calibration.

• Analytical formulae of self/mutual

inductance for quick estimation in CAD
tools and establishing design guidelines.

• Verified with test structures.

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3D Geometry Modeling for Field Solvers
Arcadia DB
Layout Design
Probe File
Arcadia Tech. File
Paths Searching (3D Geometry)
Fasthenry Input
Inductance Value
paper presented by X. Qi at CICC. May, 2000
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Inductance reduction
)
Without grids
0.9
m
due to eddy current
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/
effects - resulting from
H
0.8
Simulation
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(
time varying magnetic

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fields.
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With grids (M1 M2)
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I

0.5
p
Measurement
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0.4
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Spacing between Signal Line and Ground Line (
m)
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Analytical Formulae for MutualInductance (CICC
paper--see Publications)
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(1)
(2)
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(3)
(4)
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Case 4
(5)
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Analytical Formula for Coplanar
Waveguide Structure
L Inductance per unit length
width of the signal/
.w
, w
sig
gnd
ground wire.
thickness of the metal layer,
t
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Summary
The growing impact of inductance of on-chip
interconnects in terms of delay and cross talk

• Need close ground returns, co-planar waveguide
  shielding,

ground/power plane or grids (reduce inductance by
half).

• Good conductivity of the substrate reduces
  inductance (18

for large signal ground spacing). The three
critical factors
spacing, height of signal lines and substrate
conductivity.

• Geometry generation from layout needs to be
  integrated into

CAD tools for whole chip inductance extraction.
Derived formulae verified by experiments
demonstrate accuracy for design and CAD tools.
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Publications
On-chip inductance modeling
X. Qi, B. Klevland, Z. Yu, S. Wong, R. Dutton and
T. Young, On-chip Inductance
Modeling of VLSI Interconnects,
IEEE International Solid-State Circuits
ISSCC00
Conference
(
), pp. 172, Feb, 2000.
X. Qi, G. Wang, Z. Yu, R. Dutton, T. Young and N.
Chang, On-chip Inductance
Modeling and RLC Extraction of VLSI Interconnects
for Circuit Simulations,
CICC00
IEEE Custom Integrated Circuits Conference
(
), May, 2000.
Bonding wire modeling
X. Qi, P. Yue, T. Arnborg, H. Soh, Z. Yu, R.
Dutton and H. Sakai, A Fast 3D
Modeling Approach and Parasitic Extraction of
Bonding Wires for RF Circuits
IEDM98
IEEE International Electron Devices Meeting
, (
), pp. 299, Dec.1998.
X. Qi, P. Yue, T. Arnborg, H. Soh, Z. Yu, R.
Dutton and H. Sakai, A Fast 3D
Modeling Approach and Parasitic Extraction of
Bonding Wires for RF Circuits
IEEE Transactions on Advanced Packaging
.
Aug. 2000.
On-chip capacitance modeling
X. Qi, S. Shen, Z. Hsiau, Z. Yu, and R. Dutton,
Layout-Based 3D Solid Modeling
of IC Structures and Interconnects Including
Electrical Parameter Extraction,
IEEE International Conference on Simulation of
Semiconductor Processes and
SISPAD98
Devices
(
) pp. 61-64, Sept., 1998.
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A Fast Analytical Technique for Estimating Bounds
on Inductance

Yi-Chang Lu, Kaustav Banerjee, Mustafa
Celik, Robert W. Dutton Stanford
University Monterey Design Systems
Student with IBM Fellowship support through
Stanford CIS
Yi-Chang Lu et al, A Fast Analytical Technique
for Estimating the Bounds of Inductances in
High-Speed Clock Distribution Systems, paper
presented at CICC 2001
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• Motivations
• Clock skew and jitter are the two major factors
  which have impacts on the performance of high
  speed VLSI systems.
• Jitter comes from the clock generation circuits.
  Skew is caused by the clock distribution network
  (i.e. interconnects).
• Inductance effects caused by long interconnects
  are becoming increasingly important for deep
  submicron technologies. Using RC network to model
  interconnects is not sufficient to provide an
  accurate timing model for high speed
  applications.
• Accurate estimation of inductance is difficult
  without detailed physical information about
  interconnects. Thus we propose an analytical
  technique to estimate the bounds of line
  inductances a priori, to help designers
  improving the integrity of clock signals.

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• Clock Distribution Systems
• The clock wires in the clock distribution system
  are always shielded by ground wires. Magnetic
  flux linkages are small between adjacent metal
  layers.
• Clock pins are located far apart. Parallel clock
  wires with ground shielding in between are less
  likely to serve as return paths for one another.
• Thus the clocking system can be modeled as the
  configuration shown below.

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• Partial and Loop Inductances
• Partial inductance method requires large matrix,
  high computation complexity. It is impractical to
  be included in the early phase of design cycles.
  Loop inductance approach should be used.
• Field solvers can be used to extract inductance,
  but require detailed physical information about
  the wires, hence early estimation of wire
  inductance is difficult.
• New methodology to estimate the inductance bounds
  at the early phase must be developed!

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• Lower Bound Calculation
• Minimize Lloop
• subject to the design rules
• Use Lagrange Method to solve the multi-variable
  objective function.
• The simplified Lagrangian function

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• Lower Bound Calculation
• First-order optimality conditions

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• Upper Bound Calculation
• The absolute upper bound is
• To be more realistic
• maximize Lloop (i.e. minimize -Lloop)
• subject to the power grid locations.
• First-order optimality conditions

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Results and Applications

• Step response of an RLC network with different
  inductance values.

• Comparisons between analytical method and
  Fasthenry

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• Applications
• Inductance bounds can be used as inputs in
  simulations to generate the central moments of
  the transfer function for the RLC line.
• Inductance is not an issue when
• The clock network has severe inductance effects
  such as overshooting when
• Other cases imply that the step response is
  over-damped but the delay is affected by the
  inductance.

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• Conclusions
• An analytical model using the Lagrange Method for
  estimating upper and lower bounds of on-chip
  clock wire loop inductance is proposed.
• The ratio between the maximum and minimum
  possible value of the loop inductance is within 4
  for a 0.18mm technology.
• By using these inductance bounds, the second and
  third central moments can be calculated from
  simulations.
• These moments can be used as design metrics to
  ensure integrity of the clock signal at the early
  design phase.
• Acknowledgement MARCO Interconnect Focus Center,
  Stanfords CIS, IBM (FMA), and Monterey Design
  Systems.

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Geometric Modeling Tool-Boxfor Building
Interconnect Structures

N. Wilson, K. Wang, Dan Yergeau and R.W. Dutton
Center for Integrated Systems

• Stanford University

Staff
further documentation, see www-tcad.stanford.edu
and download the ACADEMIA Final Report

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Geodesic Software Tool-Box
Geodesic is an extensible software framework
applicable to interconnect analysis originally
developed to construct geometry for the numerical
simulation of micro-electro-mechanical systems.
Its unique features include

• Integrated multi-dimensional level set kernel
• Generic solid modeling interface
• User-selectable algorithms for etching and
  deposition to achieve multiple levels of physical
  accuracy
• Integrated automatic tetrahedral mesh
  generation (using MEGA)

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Geodesic Example Interconnect Structure
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Examples of Geodesic Geometric AlgorithmsBasic
features for solid geometry modeling
Offset solid algorithm for idealized deposition
Offset solid algorithm used for idealized
reactive ion etching
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Geodesic Advanced FeaturesDeposition / Etching
Simulation using the Level Set Method(a tool-box
capability for generalized geometry
manipulations)
Deposition Conformal deposition over corner
Etching Selective etch through a mask
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Examples of Mesh Generation (commercial code not
part of Geodesic)

• Generated directly from solid model
• Tetrahedral elements can conform to arbitrary
  geometry

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