A case study of test program generation

1
A case study of test program generation

• J. M. Martins Ferreira
• FEUP / DEEC - Rua Dr. Roberto Frias
• 4200-537 Porto - PORTUGAL
• Tel. [phone] / Fax [phone]
• (jmf_at_fe.up.pt / http//www.fe.up.pt/jmf)

2
Objectives

• To present practical BS test problems through a
  real case study
• To analyse the implementation of the test
  protocol using the test instruction set proposed
  earlier
• To enable the student to acquire the necessary
  experience to develop small test programs for
  specific test situations
• To enable hands-on sessions

3
Outline

• The demonstration board
• The information required for test program
  generation
• The test vectors
• The test program

4
The demonstration board
5
BS infrastructure
6
Full-BS interconnects (1)

• Number and identification of the BS chains
• Is the interconnect tied to GND or VCC?
• For output pins
• Number of output pins and location of the output
  cell, the control cell (if any) and the tristate
  control value
• For input pins
• Number of input pins and location of the input
  cell

7
Full-BS interconnects (2)

• For bidirectional pins
• Number of bidirectional pins and location of the
  output cell, the input cell, the control cell and
  the tristate control value
• For primary input pins
• Number of primary inputs, identification and
  tristate control value
• For primary output pins
• Number and identification of primary outputs

8
The IC1IC2 non-BS cluster
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Test of IC1IC2 (1)
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Test of IC1IC2 (2)

• HILO generated 5 test vectors to provide 100
  fault coverage of stuck-at pins in both components

11
The IC6 non-BS cluster
12
Test of IC6 (1)
13
Test of IC6 (2)

• HILO generated 5 test vectors to provide 100
  fault coverage of stuck-at pins in IC6

14
The BS components
15
The test vectors

• A modified version of the self-diagnosis
  algorithm generated 6 test vectors for complete
  short-circuit fault detection in the 24 full-BS
  interconnects

16
The serialised test vectors
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The test program
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Detection of open circuit X1

• What are the conditions enabling the detection of
  open circuit X1?

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JTAGercode (X1)

• start
• seltap0
• rst
• state irshift
• ld cnt,16d ! two IRs
• nshf 0h ! EXTEST instruction
• state drshift
• ld cnt,18d ! length of the BSR (IC3)
• nshf 02000h ! /1G0,1Y10,1Y21,1Y40 (in IC3)
• state drshift
• ld cnt,18d ! length of the BSRs
• ! Notice that we will shift only 18 bits, but
• ! - the bitstream shifted in goes to the BSR of
  IC3
• ! - the bitstream shifted out comes from the BSR
  of IC4
• nshfcp 0h,00400h,00400h ! check 2A3 when
  1Y21 set 1Y20
• jerr faulty
• state drshift
• ld cnt,18d ! length of the BSR (IC4)
• nshfcp 0h,0h,00400h ! check 2A3 when 1Y20

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Detection of open circuit X1
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Detection of short circuit X9

• What are the conditions enabling the detection of
  X9?

22
JTAGercode (X9)

• start
• seltap0 ! the test vector is applied via TAP0
• rst
• state irshift
• ld cnt,8d ! length of the IR (IC3)
• nshf 0h ! EXTEST instruction
• state drshift
• ld cnt,18d ! length of the BSR (IC3)
• nshf 40000h ! /2G0,2Y20,2Y31,2Y40 (in IC3)
• state drselect ! test vector applied on passing
  UPD-DR
• seltap1 ! response capturing is via TAP1
• rst
• state irshift
• ld cnt,8d ! length of the IR (IC5)
• nshf 0h ! EXTEST instruction
• state drshift ! test response captured on
  passing CAPT-DR
• ld cnt,18d ! length of the BSR (IC5)
• nshfcp 0h,00400h,00400h ! check if
  2A2,2A3,2A4 are 0,1,0

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Detection of short circuit X9
24
Detection of short circuit X9
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Detection of short circuit X16

• What are the conditions enabling the detection of
  X16?

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JTAGercode (X16)

• start
• seltap0
• rst
• state irshift
• ld cnt,16d ! length of the IRs (IC3,IC4)
• nshfcp 0h,8080h,8080h
• jerr faulty
• state reset
• halt ! stop here if X16 is not shorted
• faulty
• state reset
• halt ! stop here if X16 is shorted

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Detection of short circuit X16
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Detection of short circuit X16

• What would happen if only the first 8 bits were
  shifted out? (instead of 16)

ld cnt,8d ! length of the IR (IC4) nshfcp 0h,80
h,80h