Modular SOC Testing With Reduced Wrapper Count

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Modular SOC Testing With Reduced Wrapper Count

• Qiang Xu Nicolici, N., Modular SOC testing with
  reduced wrapper count, IEEE Transactions on
  Computer-Aided Design of Integrated Circuits and
  Systems, Dec. 2005, Page(s) 1894- 1908.

Presented By Yuyan Xue (April. 2007)
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Motivation

• Modular test strategies (Wrapper, dedicated
  bus-based TAM) enable the reusability,
  scalability and interoperability in DFT.
• Modular test strategies add the overall cost of
  the test.
• Modular test strategies deteriorate the system
  performance if they stand on the critical path.

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Objective

• Reduce the wrapper count, meanwhile maintaining
  the benefits of modular SOC testing.
• Compatible to IEEE P1500 standard, meanwhile
  investigate the suitability of reusing the
  functional interconnect for transferring test
  data

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Idea from IEEE P1500

• INTEST/EXTEST
• Producer/Consumer
• A core can be tested without wrapping its
  terminals as long as all its producers and
  consumers are P1500-wrapped.

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New Wrapper Design for Embedded Cores

• No wrapper at all (INTEST/EXTEST modes only)
• Light wrapper without WBR (RAM/ROM for BIST)
• Parallel Bypass Register (WBY)
• Revised P1500 Wrapper for P/C cores.

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New Test Conflicts Caused

• Traditional TAM lines conflict in IEEE P1500
• New test conflicts
• Producer-CUT
• Core6-gt2,5,9
• CUT-Consumer
• Core2-gt6,7,8,9
• Shared-Producer
• Core7,8-gt2
• Shared-Consumer
• Core3,6-gt5
• Shared-Bus
• Core1,5-gt8

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TAM Division Into Three Groups

• Flexible-width test for GCUT
• Daisy chain for Gprod and Gcons

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Wrapper/TAM Co-optimization

• Given PIs, PIOs, bidirectional I/Os, test
  patterns, scan chains and scan chain length,
  total TAM width, wrapper design constrains
• Output the width of each TAM group, wrapper
  design for each core, the test schedule
• Satisfy wrapper design constrains, maximized
  light-wrapper number, TAM width constrains,
  minimized overall SOC TAT

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Three Types of Wrapper Design Constraints

• Critical Path -gt Light wrapper
• Cores with P1500 wrapper provided
• Two-pattern tested ( delay and stuck-at fault)

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TAM Division and Test Scheduling Algorithm

• Determine light-wrapped cores lt-functional
  interconnection wrapper design constraints
• Create Test Incompatible Graph (TIG)
• Enumeratively find the optimal TAM division and
  the minimum system TAT.
• Worst case complexity

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Decide Wrapper Type

• Given the set of cores, the functional
  interconnect relationship, wrapper design
  constrains
• Output wrapper type for each core
• Methodology
• Wrapper status initialization ( wrapper
  constraints)
• Light-wrapped as default and compute test
  dependency.
• Choose cores with less test dependency

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Construct TIG

• Given the set of cores, test conflicts
• Output node for core and edge for conflicts
  between two cores
• Conflicts only exist between
• Two light-wrapped cores
• A Light-wrapped core and
• its producers/consumers

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Dynamic Rectangle Representation

• Rectangle representation for P1500-wrapped core
• Rectangle representation for light-wrapped core

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Adaptive Dynamic Rectangle Packing

• Given the set of cores, TIG, TAM division
• Output schedule for each core, overall TAT of
  the SOC
• Methodology
• Find out pareto-optimal TAM width
• Schedule cores using the preferred width, as long
  as TAM width is sufficient
• Pack the idle time with remaining test
• Repeat scheduling process for remaining test if
  one test is completed

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Experimental Result
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Experimental Result (Continued)
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Contributions

• Light-wrapped core is introduced to reduce the
  number of wrapper cells in the SOC without
  impacting its testability. Up to half of the
  cores can be unwrapped without affecting the test
  quality.
• New modular SOC test architecture is proposed,
  which employs three separate TAM groups and
  facilitates concurrent testing of both
  P1500-wrapped cores and light-wrapped cores.
• New algorithms for wrapper/TAM co-optimization
  and test scheduling is introduced.