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VTB Pro Modeling Language

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Eliminate tedious and error-prone process of component ... ASIN. ACOS. ATAN. SINH. COSH. TANH. EXP. LOG. LOG10. SQRT. ABS. RAND. CEILING. FLOOR. MAX. MIN. MOD ... – PowerPoint PPT presentation

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Title: VTB Pro Modeling Language


1
VTB Pro Modeling Language
Roger Dougal, Eugene Solodovnik, Blake Langland,
Earnie Broughton Department of Electrical
Engineering University of South Carolina
VTB 2005 University of South Carolina
University Columbia, South Carolina September
20 2005
2
VTB Pro Modeling Language Goals
  • Eliminate tedious and error-prone process of
    component development by hand
  • Rapid development of components for simulation
  • Computational performance of the components
  • Support for development of complex components
    linear or nonlinear, natural or signal
  • Support for advanced lingual structures such as
    IF-THEN-ELSE Statements
  • Extensible
  • No C, C, C, etc. coding needed to develop a
    component

3
UDD to VTB Pro Language
  • Unlike UDD, VTB Pro Language is integrated into
    VTB Pro Framework
  • VTB Pro Language is used not only for component
    model creation, but also for component parameter
    validity checks, in VTB Pro UDD components, in
    VTB Pro Signal Output Generator, etc.

VTB Pro Language
VTB Pro Component Builder
4
VTB Pro Language
Across Variables
Through Variables
  • Supports Initial conditions
  • Supports Switching component models
  • Supports natural, signal or mixed components
  • Supports component parameters range of validity
    checks
  • Automatically detects if component model is
    linear, nonlinear or time dependent for
    generation of the most efficient code

5
Applications of the Modeling Language in VTB Pro
  • VTB Pro Component Builder
  • -Allows to define component model before it is
    used in VTB Pro Studio
  • VTB Pro User-Defined Device (UDD) components
  • -Defines component model during the VTB Pro
    Studio run time
  • VTB Pro Signal Output Generator (SOG) component
  • -Allows to create Signal output as an arbitrary
    function of any viewables, parameters, variables
    of any components in a system

6
VTB Pro Language
Natural component
Structure of the input language
Plus
Minus
Example
Ron PARAMETER(Ron) G 1.0/Ron
Identifiers
DEFINE_THROUGH(Plus) G (GET_ACROSS(Plus) -
GET_ACROSS(Minus)) DEFINE_THROUGH(Minus) -G
(GET_ACROSS(Plus) - GET_ACROSS(Minus))
Equations
cos
Output
Input
Signal component
DEFINE_SIGNAL(Output) SET_SIGNAL(Output,
COS(GET_SIGNAL(Input)))
Equations
7
VTB Pro Language
If-Then-Else Example
Ramp Signal Generator
DEFINE_SIGNAL(Output) IF (TIME() lt
PARAMETER(StartTime)) SET_SIGNAL(Output,
PARAMETER(InitialValue)) ELSE
SET_SIGNAL(Output, GET_SIGNAL(Output, 1)
TIMESTEP() PARAMETER(Slope)) IF (TIME() lt
PARAMETER(StartTime)) IF (TIME()
TIMESTEP() gt PARAMETER(StartTime))
SET_TIME_STEP(PARAMETER(StartTime) - TIME())

Access to Past History value
Output
8
VTB Pro Language
Mathematical Functions
Operations
Functions
SIN COS TAN ASIN ACOS ATAN SINH COSH TANH EXP LOG
LOG10 SQRT ABS RAND CEILING FLOOR MAX MIN MOD
PARAMETER GET_ACROSS GET_THROUGH DEFINE_THROUGH DE
FINE_INITIAL_THROUGH DEFINE_INTERNAL_NODE DEFINE_V
IEWABLE SET_VIEWABLE DIFFERENTIATE INTEGRATE
- / ! lt lt gt gt
SET_VARIABLE GET_VARIABLE DEFINE_VARIABLE DEFINE_I
NITIAL_VARIABLE SET_SIGNAL GET_SIGNAL DEFINE_SIGNA
L TIME TIMESTEP
IF ELSE
Lingual Structures
9
VTB Pro Component Builder
  • Creates and manages Components, their Icons and
    Engines in Database
  • Component Engines can be supplied as binary
    Assembly (dll) or as VTB Pro Language
  • To create binary Assembly, the Skeleton Code can
    be generated, the model is defined later in C
  • For Engines supplied in VTB Pro Language, full C
    code of the model can be automatically generated

DEMO
10
VTB Pro User-Defined Device (UDD)
  • Defines component model during the VTB Pro
    Studio run time
  • VTB Pro Language is used
  • Currently available as natural and signal
    components
  • Allows to generate C code and MS Visual Studio
    Solution for the component

Example Nonlinear Inductor
Port1
Port3
UDD
Port2
Vs 0.1 Is 1 b 5 DEFINE_THROUGH(Port1)
Is (GET_ACROSS(Port3) / Vs)b DEFINE_THROUGH(Po
rt2) -Is (GET_ACROSS(Port3) /
Vs)b DEFINE_THROUGH(Port3) DIFFERENTIATE(GET_A
CROSS(Port3)) - (GET_ACROSS(Port1) -
GET_ACROSS(Port2))
DEMO
11
VTB Pro Signal Output Generator (SOG)
  • Allows to create Signal output as an arbitrary
    function of any viewables, parameters, variables
    of any components in a system

Example
ABS(R1.Voltage L1.Current) VS1.Power
DEMO
12
Current and Future Work
  • Extensions to modeling language by adding more
    functions, differentiating conditional
    expressions and some non-continuous mathematical
    functions
  • Enable Gears 2 integration method
  • Integration with Scripting Tool to provide
    greater control over the simulation scenarios
  • Run time processing and post processing of
    simulation data through language extensions.
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