System-On-a-Programmable-Chip (SOPC) Implementation of the Silicon Track Card (STC)

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System-On-a-Programmable-Chip (SOPC)
Implementation of the Silicon Track Card (STC)

• Thesis Defense
• ByArvindh-kumar Lalam
• Department of Electrical and Computer Engineering
• Florida AM University Florida State University
  
• College of Engineering

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Outline

• DZERO Experiment
• Silicon Track Card (STC)
• SOPC Implementation and Validation
• Content Addressable Memory (CAM)
• Hit-Filter Implementation using a CAM
• Results and Conclusions

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Proton Anti-proton Collision

• Study the properties of known particles
• Eg. top quark
• Look for the unknown

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DZERO (D0) Experiment

• The DZERO Experiment is conducted in Tevatron
  Collider, at Fermi National Acceleration
  Laboratory
• proton anti-proton are made to collide at high
  velocities in the TeVatron collider
• The beams cross every 132 ns

The TeVatron Collider
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D0 Detector
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Particle tracks

• Cross-section of Fiber Tracker (CFT)

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D0 Trigger
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The Level_2 STT
L3
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D0 Trigger -
STC

• road Track information translated for the
  STC

• clusters Groups of strips

• centroid Centroid of a cluster

• hit A centroid that falls in a road

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STC - Functionality

• Reformats received strip data
• Finds Clusters and their centroids
• Identifies hits
• Stores intermediate data for debugging
• Implements a contention scheme
• Several STCs function simultaneously
• Operates at PCI 33 MHz

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STC - Main Data Path
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Control Logic and Channels

• Control Logic designed at BU acts as an interface
• Each Control Logic controls 8 Channels (STCs)
• STC receives SMT data directly from SMT
• commom data bus is used to download hits

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System-On-a-Programmable-Chip (SOPC)

• Discrete PCB components?
• SOPC
• Altera APEX II EP2A90
• 7M gates 1.5Mbits SRAM
• Xylinx Virtex E XC2V10000
• 10M gates 3.4 Mbits SRAM
• Altera APEX 20KE
• EP20K600EBC652-1X
• Accommodates 1 STC

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SOPC - Advantages

• The circuit can be fit into a single device
• Occupies smaller area on the board
• Board-design interconnects are less complex
• Internal propagation delays are predictable

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Computer Aided Design Tools

• Entry and Functional Simulations Quartus II,
• Active HDL 4.2
• Entry in VHDL/Schematics
• Synthesis Quartus II, Synopsys FPGA Express
• Simulation and Configuration Quartus II

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SOPC Implementation of STC

• Control Logic
• BU
• Silicon Track Card
• FAMU-FSU COE
• Used Test memory
• space to store test
• vectors of SMT data

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SOPC Implementation - Hit download
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SOPC Implementation - Result
Channel Hits Trailers Hit-words
STC0 7 1 8
STC1 2 1 2
Contention is successfully resolved
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STC - Resources
Device Family Chip Logic Elements Memory bits Pins
FLEX (CPLD) EPF10K100EBC356-1 4,340 (83) 10,532 (21) 257 (94)
FLEX (CPLD) EPF10K200EGC599-1 2,941 (29) 79,424 (80) 466 (99)
FLEX (CPLD) EFF10K200SFC484-1 1,860 (18) 10,692 (10) 292 (79)
FLEX (CPLD) Total 10,361 96,612 829
APEX (SOPC) EP20K600EBC 652-1X 6,744 (27) 105,828 (33) 262 (53)
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Content Addressable Memory(CAM)

• A memory like RAM and FIFO
• Takes data as input and provides the location
• Output can be encoded or unencoded
• A found signal is used to signal presence of
  data

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Dont cares

• Dont-cares can be used to represent multiple
  digital words
• A dont-care (d) represents both 1 and 0
• CAMs that accommodate dont-cares are called
  Ternary CAMs
• Eg APEX CAM

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APEX CAM

• Memory blocks of Alteras APEX chip can be used
  as a Ternary CAM
• The data can be stored in two ways
• During power-up (using an .mif file)
• During run-time

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Previous Hit Filter

• Receives roads and centroids
• Internally stores roads
• Uses hit-match modules to find if a centroid
  falls in the roads
• When a centroid falls in a road, it is a hit
• Each hit-match generates a bit 1 for hit

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Previous Hit Filter Block Diagram

• Contains 46 hit-match modules
• Each of the centroids is checked in all roads
• The locations of 1s are encoded to generate a
  hit-word
• Hit-format, designed in VHDL, uses Finite State
  Machine
• Hit-format module sequentially searches for hits.

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Hit Filter CAM-only model

• Uses memory blocks instead of a combinational
  circuit (comparator)
• Set of all the words existing between the road
  boundaries is called a road-set
• Each road-set can be minimized to 12 words by
  using dont cares
• road-sets of each road are stored in the memory

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Minimized Road-Set
1000 0000001 . . 1000 1111110
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CAM-only model Implementation
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CAM-only Model - Functionality

• Storing roads
• The road-set is minimized by using the dont
  cares
• The minimized road-set is stored in an APEX CAM
• The CAM needs 50 clock cycles to store each
  road-set
• Checking for hits
• Each of the centroids is given as input to the
  CAM
• If the centroid is found in the road-set, CAM
  returns all the encoded locations.
• CAM takes only two clock cycles to find the
  location of first hit

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Hit Filter With New Encoder

• Uses previous comparator block and a new
  hit-word generator block
• The locations of 1s in the comparator word are
  encoded using a CAM

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Hit Filter Implementation
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CAM as Encoder
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Hit Filter Encoder Map
46 x 46 Encoder Map
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Hit-Word Generator
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Hit Filter Results
Number of clock cycles required for storing road
information
6 roads (consecutive) 6 roads (distributed) 46 roads
Sequential search (contains comparator) 6 46 46
CAM only 270 310 2070
With CAM block in hit-word generator (contains comparator) 6 46 46
This depends on the upper and lower words of
the road. The quoted figures correspond to the
worst possible case.
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Hit Filter Results
Number of clock cycles required for finding hits
6 roads (consecutive) 6 roads (distributed) 46 roads
Sequential search (contains comparator) 32 150 232
CAM only 10 10 50
With CAM block in hit-word generator (contains comparator) 10 10 50
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STC Results

• Event 1 SMT data for a simple event
• Event 2 SMT data for a complex event

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Conclusions

• SOPC implementation was successfully verified
• The upgraded STC shows an improvement of upto
  87

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Future Work

• The number of roads Hit-Filter can accommodate
  can be increased

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Acknowledgements

• National Science Foundation and the US Department
  of Energy.
• Boston University
• Faculty Heintz, Narain, Popkov
• Engineers Earle, Hazen
• Students Kevin, Zabi
• Florida State University Physics
• Faculty Adams, Prosper, Wahl
• Postdocs Tentindo-Repond
• Florida AM University Florida State University
  COE
• Faculty Perry
• Students Lolage, Meyers, Roper, Saunders
• Altera, Aldec, Synopsys