Scaled CMOS

1
Scaled CMOS Radiation 06-080(Continuation
FY06)
Description
FY06 Plans

• In FY06, we seek test vehicles from amongst the
  following
• Texas Instruments (charge collection and TID) in
  collaboration with Vanderbilt University and
  DTRA,
• SDRAMs from Samsung (90 and 80nm),
• LSI Logic 0.11 um technology (began in FY05),
• Toshiba (90 and 65 nm)
• Freescale
• IBM (90nm) (via DARPA/DTRA), 130nm transient
  laser test,
• TSMSC 90nm test structurs (with Xilinx and AFRL),
• IMEC (collaboration with ESA),, and,
• Others.
• Leverage data analysis of FPGAs and memories

Changes in the CMOS electronics technologies are
showing new and different effects (spatial and
temporal) as well as changes in tolerance (TID
increase, for example). This task looks to
evaluate both on-shore and off-shore CMOS fabs
for scaling effects and radiation. For purposes
of this task, we consider feature sizes ranging
from 130nm to 45nm. All tests are pending device
availability. Tests include Co-60 (TID),
microbeam (charge collection), heavy ion single
event effect (SEE), laser SEE, and proton (SEE
and damage). We shall also leverage tests from
related tasks on FPGAs and memories.
Total Full-Cost 500K
Schedule/Costs
Deliverables

• Test Reports (2-4 weeks post-test)
• Quarterly Reports
• TBD Technical papers documenting results (IEEE
  NSREC, SEE Symposium)

NASA and Non-NASA Organizations/Procurements
Industry - Xilinx, TI, Samsung, Freescale all
are partners - ATK/MRC University - Vanderbilt
University Other Government - DTRA, AFRL, MDA,
NAVSEA Crane, DARPA, NRL, ESA TBD Beam
procurements (TAMU, IUCF, other) and test devices
Lead Center/PI Ken LaBel/GSFC Co-Is Christian
Poivey/MEI Center Funding Split GSFC - 500K