EE272 Synthesis and Place and Route

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EE272Synthesis and Place and Route

• Ken Mai, Elad Alon, Francois Labonte

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Overview

• Synthesis
• When to use it
• Steps
• How to use it
• Demo
• Place and Route
• Place and route of standard cells
• Demo
• Global Place and Route
• Demo

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Synthesis When to use it

• Theoretically you could layout the whole chip
  using magic
• Then again you might want to do something else
  than layout in this lifetime.
• Datapaths (multiple bits with symmetry) can be
  efficiently done
• the dataflow is logical and planned
• cells are highly replicated worth the effort
• Random (control) logic would be a pain to layout
• Most cells exist only once
• The connections are all over the place
• You will want to synthesize your control block

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Steps

• Synopsis Design Analyzer (Synthesis Tool) will
  churn the Verilog into a Netlist connected with
  gates and latches(trying to minimize the gates
  hopefully)
• We can then convert this netlist into Sue
  schematics (v2sue) to simulate the transistors
• In the place and route tool (Snake) We can
  instantiate the standard cells within a block of
  a shape of our choice
• Then we can route in between the standard cells
• Finally to link up with the datapath weve
  customed layed out, we instantiate the datapath
  and route between the controller and the datapath

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Synopsys Design Analyzer

• To Start Design Analyzer
• gt design_analyzer
• File gt Read File (your verilog controller file)
• Look at the report!!!
• Check for inferred latches You should NEVER
  have inferred latches

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Inferred Latches in Combinatorial Logic

• BAD
• // Using if-then-else statements
• //
• always (_at_enable)
• if (enable 1b1)
• out 1b1
• // Latch with enable as clock and out as input
• // Using case statements
• reg 10 state
• always (_at_state)
• case (state)
• 2b0 out 1b1
• 2b2 out 1b0
• 2b3 out 1b0
• endcase

• GOOD
• always (_at_enable)
• if (enable 1b1)
• out 1b1
• else
• out 1b0
• always (_at_state)
• case (state)
• 2b0out 1b1
• 2b1 out 1b0
• default out 1b0
• endcase

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Inferred Latches duplicated

• Assigning a register in 2 different always block
  is a BAD IDEA
• Synopsys will generate 2 latches and combine the
  ouputs with gates
• Put everything in one always block sensitive to
  all inputs

• BAD
• // Reset Logic for state bits in separate always
  block
• //
• always (_at_Reset) // Combinational Logic
• if (Reset 1b1)
• state 3b0
• // Normal next state logic
• //
• always (_at_Phi1 or opcode or state)
• if (Phi1)
• case (state)
• STATE1
• state STATE2

• GOOD
• // Next state logic
• //
• always (_at_Reset or Phi1 or opcode or state) //
  Combinational Logic
• if (Reset 1b1)
• state 3b
• else
• case (state)
• STATE1
• state STATE2
• ...
• ...

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Verilog Case Statements

• Case Statements come in 4 synopsys flavours
• Parallel you are sure only one of the states is
  true (so the order in which they are evaluated is
  not important)
• Full case all the possible states are in the
  case statements (no omission or default)
• Parallel and Full case
• Neither order is important (generate circuit
  slower and more bloated usually)
• Synopsys assumes by default neither parallel or
  full

case (state) // synopsys parallel_case STATE1 -
-------------------------- case (state) //
synopsys full_case STATE0.... ------------------
------------- case (state) // synopsys
parallel_case full_case STATE0...
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Demo

• Do HW2 and HW3

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Place and Route of Std Cells

• Standard Cells have the same bit pitch to have
  adjacent power wire.
• Their connections stick out on the bottom and top
• The place tool will put them in rows spaced with
  routing channels
• Their location is not always optimal long wires

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Snake

• Our place and route tool is called snake
• Make sure csnake.ini is in the working directory
  (copy from /usr/class/ee272/snaketech/etc/csnake.i
  ni
• gt xcsnake
• First thing we will do is place the gates of our
  controller and route connect them together
  (please do HW3)
• Inputs and outputs to our controller will be
  connected to the datapath or pads
• To tell Snake where we would like these
  controller I/Os to be we need to make a

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Telling Snake Where Controller I/Os are desired

• This is from HW 3 Just do it
• The first line of csnake.ini specifies the
  termcoordfile, modify it accordingly otherwise
  your I/O will be all over the place
• UNITS GRID OR UNITS MICRON
• ORIGIN CORE OR ORIGIN CHIP
• ltterminal node namegt ltsidegt
• ltterminal node namegt ltX-coordgt,Y-coordgt
• ltterminal node namegt ltX-sidegt,Y-coordgt
• ltterminal node namegt ltX-coordgt,Y-sidegt
• Basically you can specify an exact location, a
  side or

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Demo

• Part of HW3

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Global Place and Route

• We are going to connect a custom datapath to a
  synthesized controller
• First step is to prepare the datapath layout to
  be connected to the controller 2nd part of HW 2
  DO IT!!!
• The I/Os need to be touching the outside of the
  datapath (we dont want snake to route over your
  datapath, it would short stuff)
• The I/Os need to be labeled on the magic toplevel
  file of your datapath (need metal at that
  toplevel
• The labels need to be yellow boxes, not just
  (Dont ask me why)

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Global Route

• HW 2
• Ports2edif is broken, its a perl version
  problem Ill be looking into it
• Too bad you wont be able to do all of HW 2
  immediately -)