Amol Bakshi, Jingzhao Ou, and Viktor K. Prasanna - PowerPoint PPT Presentation

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Amol Bakshi, Jingzhao Ou, and Viktor K. Prasanna

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driving design space exploration tools for rapid evaluation of a ... Tradeoff analysis and design space exploration. Kernel application. Energy-efficient design ... – PowerPoint PPT presentation

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Title: Amol Bakshi, Jingzhao Ou, and Viktor K. Prasanna


1
An Integrated Design Environment to Evaluate
Power/Performance Tradeoffs for Sensor Network
Applications
  • Amol Bakshi, Jingzhao Ou, and Viktor K. Prasanna

Dept. of Electrical Engineering -
Systems University of Southern California
Los Angeles, CA
Project URL http//milan.usc.edu/
funded by the DARPA Power-aware Computing and
Communications program
2
MILAN A Model-based Integrated Simulation
Framework
  • A unified environment capable of
  • modeling a large class of embedded systems and
    applications
  • driving design space exploration tools for rapid
    evaluation of a large design space
  • seamlessly integrating different widely-used
    simulators into a single framework for
    hierarchical simulation
  • enabling rapid evaluation of different
    performance metrics such as energy, latency, and
    throughput
  • Use coarse system models based on key parameters
  • Reduce initial design choices
  • Use low-level simulators to analyze the reduced
    design options
  • Choose one (or more) designs for implementation

3
Design Flow in MILAN
Application (Task Graph)
Hardware Resources
4
I. Energy-Efficient Design of Sensor Network
Applications
  • A modeling and simulation environment for
    power-aware design of a multi-node sensor network
  • Multi-granularity simulation
  • Simulator integration
  • Results from Wattch simulation are used to
    automatically configure ns-2 parameters
  • Results from Wattch/ns-2 are used to
    automatically refine parameters for high-level
    estimator

5
II. Energy-Efficient Design of Kernel
Applications for FPGAs
EAT (million nJ?slices?cycles) EAT (million nJ?slices?cycles) EAT (million nJ?slices?cycles) EAT (million nJ?slices?cycles)
Matrix Size Xilinx Uni-proc. Linear Array
3 ? 3 0.2 0.1 0.1
6 ? 6 41.2 3.9 3.5
9 ? 9 469.5 39.2 32.5
15 ? 15 10063.3 839.77 580.0
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