SWAN: System for Wearable Audio Navigation

1
SWAN System for Wearable Audio Navigation
Mapping A Visual Environment to a 3D Audio
Soundscape
Tom Cheng Stuart Duerson Shaun Thamer
PHASE I ECE 4180 ECE 4180 FALL 2004
2
Idea

• Create a 3D visual model of an area
• using various methods.
• Create hardware so that a person can navigate
  the area using audio
• cues as a guide.

• This hardware must perform several tasks
• a.) Visually recognize the mapped area from any
  angle.
• b.) Extract meaningful visual
  information.
• c.) Produce meaningful auditory cues for the
  user to
• respond to.

3
Our Tasks
ECE 4180

• Implement the visual recognition
• Harris Corner Detection Algorithm
• On a Xilinx Spartan II FPGA

ECE 4006

• Integrate four cameras with custom PCB.
• Integration with sonification backend.

Our Advisors
Prof. Bruce Walker
Prof. Frank Dellaert
4
Objective
Our Goal for 4180

• Implement Harris Corner Detection Algorithm with
  Xilinx IP Cores,
• Optimize the design, and implement it on a Xilinx
  FPGA

Why is the algorithm useful?

• The Harris Corner Detection
• Algorithm is able to extract key
• features of an image for purposes
• such as image recognition, etc.

- This heavily factors into the end goal of SWAN.

5
Harris Step -by-Step
Gaussian Smoothing
X-derivative
Original
Y-derivative
XY-derivative
Result
Some Math
6
Project Step-by-Step

• Step 1 Understand the algorithm
• Step 2 Create MATLAB m-files implementing the
  algorithm
• Step 3 Create reference Simulink implementation
• Step 4 Create Gaussian smoothing FIR filter
• Step 5 Optimization
• - Cut down on multipliers by using time-slice
• multiplexers.
• - Use smoothing kernel with power of two
• coefficients.
• Perform iterations on the optimized Simulink
• design to match the m-file implementation.

7
Comparison
Ideal
Implementation
8
Achieved

• Simulink implementation of the Harris algorithm.

• Successful simulation of algorithm in simulink.
• Area estimate for FPGA implementation.

Problems

• Unresolved timing constraint in synthesized VHDL
  file.
• Difficulty in fitting 7 coefficient Gaussian
  onto FPGA.

9
Area
- How much space does the design take up?
Flip-Flop Utilization
FPGA Capacity
Best Simulation 158
Best Area 52
Best Simulation Implementation Has 7
coefficient smoothing Gaussian and finds most
corners. Best Area Implementation No smoothing
Gaussian, fits on FPGA, buts misses corners.
10
PROJECT TIMELINE
ACTUAL TIMELINE