Technical%20Report

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Technical Report
High Speed CMOS A/D Converter Circuit for Radio
Frequency Signal
Kyusun Choi
Computer Science and Engineering Department The
Pennsylvania State University
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Project Goals
Core development and silicon test of 6 and 8 bit
TIQ based flash ADC

• High speed circuit and layout design
• 2. Prototype chip fabrication
• 0.25um and 0.18um CMOS
• 3. Test and evaluate, explore and improve

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Project Milestones

1. 1st Chip design, 0.25um 12/01/2000
2. Chip fabrication 02/05/2001
3. Chip testing 04/04/2001 1st report
4. 2nd chip design, 0.18um 07/10/2001 2nd
   report, chip
5. Chip fabrication 10/08/2001
6. Chip testing 11/09/2001 3rd report
7. Project ending 12/31/2001 Chip
8. Project presentation 02/15/2002 Final report

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Project Feature

1. High speed ADC, 1 GSPS
2. RF applications
3. SOC applications, digital CMOS
4. Future-ready, lt 0.10um, lt 1.0V

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TIQ flash ADC
6
Other flash ADC
V1
Vref

Vin
R
V2
V1

R
D1
D2
V3
V2
D3

R
V3
Dk

R
Vn
Vn
Thermometer code to binary encoder
Resistor ladder circuit
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TIQ comparator
DIFFERENTIAL INPUT VOLTAGE COMPARATOR
INVERTER
Vr is provided by a voltage references
source, External to the voltage comparator
Vm is an internal parameter of an inverter, fixed
by the transistor sizes
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TIQ comparator

• High speed
• Less area
• No resistor ladder and reference voltages
• No capacitor switching
• Future ready
• Scale down
• Low supply voltage
• Standard digital logic technology
• Ideal for SOC

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Prototype Test Results
1st prototype chip (0.25um), six ADCs on chip
ADCs Precision Delay Power
6bit0.25 4 bits 3.799 ns 109.38
6bit1.00 6 bits 21.404 ns 35.25
8bit0.25 5 bits 7.249 ns 170.50
8bit0.50 7 bits 18.612 ns 121.25
9bit0.50 6 bits 27.762 ns 200.375
9bit1.00 8 bits 83.595 ns 179.625
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Prototype Test Results
2nd prototype chip (0.18um), ten ADCs on chip
ADCs Precision Delay Power
6bit1.00FAT 6 bit 2.65 ns 27.0 mW
6bit1.00ROM 6 bit 4.50 ns 21.6 mW
6bit0.50ROM 3 bit 2.97 ns 36.0 mW
6bit0.18ROM 3 bit 3.35 ns 77.4 mW
8bit1.0ROM 6 bit 15.45 ns 64.8 mW
8bit0.50ROM 5 bit 6.65 ns 75.6 mW
9bit1.50ROM 5 bit 29.20 ns 64.8 mW
9bit1.00ROM 5 bit 36.50 ns 111.6 mW
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Prototype Test Results
ADC 6 bit 1.00um, ROM, 0.18um prototype
chip Input 100 KHz Saw wave
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Prototype Test Results
ADC 6 bit 1.00um, FAT, 0.18um prototype
chip Input 100 KHz Saw wave
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Prototype Test Results
ADC 9 bit 1.00um, ROM, 0.25um prototype
chip Input 100 KHz Saw wave
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Prototype Test Results
ADC 6 bit 1.00um, FAT, 0.18um prototype
chip Input DC
DNL 0.36 LSB INL
1.36 LSB
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Prototype Test Results
ADC 6 bit 1.00um, FAT, 0.18um prototype
chip Input 80KHz sign wave, f_sample 10 MHz
SNR 23.40 dB SNDR 21.83 dB SFDR 9.13
dB ENOB 3.33 bits
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Prototype Test Results
ADC ideal 6 bit Input 1MHz sign wave,
f_sample 200 MHz
SNR 37.78 dB SNDR 36.56 dB SFDR 37.86
dB ENOB 5.78 bits
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Summary

• High speed ADC for RF application
• ADC core - 6 and 8 bit design
• prototype chips (silicon test)
• 0.25 ?m and 0.18 ?m
• CMOS digital logic technology
• SOC beyond 0.10um 1.00V

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Innovation/enhancement challenges

• 1 GSPS with digital CMOS
• Custom layout generation and
• modeling CAD tool
• 8bit and 10bit ADC
• Low power
• Low noise
• Dynamic calibration
• Offset
• Gain
• Temperature
• Power supply voltage
• Process parameter variation

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Summary

• High speed ADC for RF application
• ADC core - 6 and 8 bit design
• prototype chips (silicon test)
• 0.25 ?m and 0.18 ?m
• CMOS digital logic technology
• SOC beyond 0.10um 1.00V

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Chip1 6bit 1.00um, A120KH Sine Input A2 Vdd,
w/o R on Probs
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Chip1 6bit 1.00um, A1 20KH Sine Input A2 Vdd w/
4.7K Ohm on Probs
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Chip1 6bit 1.00um, A1 20KH Sine Input A2 Vdd w/
R on Probs
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1st Prototype Chip Test Board
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2nd Prototype Chip Test Board