Scaling of OCDMA switch

1
Scaling of OCDMA switch

• Herwin Chan

2
Current System
BP
16X16 Switch
116
161
2.5Gbps
155Mbps
2.5Gbps
16X16 Switch
116
161
U
116
161
16X16 Switch
16X16 Switch
116
161
B

• Each input user bit has 16 degrees of freedom
• AES is not implemented as code generator

3
Equivalent System

• Functionally the same as the previous system
• Communication between devices are at a higher rate

2.5Gbps
2.5Gbps
620Mbps
14
41
41
14
16X16 Switch
41
14
41
14
4
System Parameters

• Parallelization Factor (P)
• Decrease rate of communication between blocks
  increases hardware cost
• Block Width (B)
• Increase security level increase hardware cost
• Code Update Interval (C)
• Decrease security level decrease hardware cost

These two factors determines the amount of
serialization / deserialization necessary
5
Scaling of Current System

• Restrictions
• 116 serializer / deserializer
• 16 lvds i/o in FPGA

6
FPGA or ASIC
7
FPGA platform

• Virtex-2 Pro Board from Xilinx
• (HW-AFX-FF1152-300)
• 8 channels of Rocket I/O (2.5 - 3.1 Gbps)
• FPGA on board

8
AES on OCDMA FGPA

• Possible to build only 1 AES block on FPGA
  (XC2VP50)
• This can supply control bits at rate of 20Gbps
• Current implementation requires
• 4 155Mbps 56 bits 35Gbps
• (assumes code update rate C 1)

9
Security Tradeoffs

• Number of users fixed (U4) by I/O limits
• Play with block width (B) and code update rate
  (C) for systems that are implementable (lt20Gbps)

Can be easily implemented with single clock system
10
Equations

• Control bits needed for arbitrary size Benes
  network
• Rate for control bits (in Gbps)