ECE 551 Final Project

1
ECE 551 Final Project

• Simon Game
• Kenneth Gilbert and Ben Rankin

2
Outline

• System requirements
• Design process
• System block diagram
• System modules
• Conclusions
• Appendix

3
System Requirements

• Implement popular memory game Simon
• Randomly create and store sequences
• Proper sequence detection
• Communicate between user and FPGA (input/output)
• Built-in self test (BIST)
• Physically map to Altera test board

4
Design Process
5
System Block Diagram
6
System Modules

• Main module
• Input module
• Random number generator
• Clock module
• Output module
• Memory module
• Built-in self test

7
Main Module

• State machine
• Intelligence of the system
• Utilizes data from the modules
• Controls game flow and status

8
Input Module

• Takes four pushbutton inputs
• Debounces raw input signals
• Converts pushbutton depressed to three-bit vector

9
Random Number Generator and Clock Module

• Random number generator
• Locked seed, but randomness based on time
  requested
• Algorithm based on polynomial x4 x3 1
• See appendix for reference

• Clock module
• Uses the simple clock_div code
• Input is 25 MHz clock from reference board
• Output is 100 Hz clock to provide more human
  speed timing

10
Output Module

• Provides method of output using to two
  seven-segment leds and four general purpose leds
• Receives signals from main module and bist
• Select bit determines default mode vs BIST mode
• Converts 3 bit led vector to appropriate led
• Converts 4 bit left and right vectors for seven
  seg

General Purpose Leds
Seven Segment Leds
11
Memory Module and BIST

• Memory module
• 128 2-bit integer indexed cells
• Read_write and enable bits stimulate transfer
• Reset signal resets values and asserts high Z out

• Built-in self test
• All general purpose leds and seven seg leds
  triggered in default mode (snake and knight
  rider)
• Depressing push- buttons displays number on seven
  seg and corresponding general purpose led

12
Conclusions

• Project was physically implemented on Altera, but
  also synthesized and fit in Xilinx
• Developing code that compiled and tested under
  ModelSim was fairly easy
• Creating synthesizable code cross platform proved
  more difficult and more unpredictable than
  expected
• Simplicity in code is often key in VHDL

13
Appendix

• Video of simon in action on cd
• Online flash simon
• Random number generator code used in project

• http//www.neave.com/webgames/simon/

• http//www.ece.uic.edu/jszczech/project/